Timing Analyzer Maximum and Minimum Delay Commands

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Minimum Delay

You can use the set_min_delay command to specify an absolute minimum delay for a given path. The following list shows the set_min_delay command, including the available options:

set_min_delay
     [-from <from list>]
     [-to <to list>]
     [-thru <thru list>]
     <delay value>

Table 1 describes the options for the set_min_delay command.

Table 1. Options Description for set_min_delay Command

Option Description
-from <from list> The <from list> is a collection or list of objects in the design. The <from list> acts as the start point of the path.
-to <to list> The <to list> is a collection or list of objects in the design. The <to list> acts as the end point of the path.
-thru <thru list> The <thru list> is a collection or list of objects in the design. The <thru list> acts as the thru point of the path.
<delay value> Specifies the delay value.

If the source or destination node is clocked, then the clock paths are taken into account, allowing more or less delay on the data path. If the source or destination node has an input or output delay, that delay is also included in the minimum delay check. When the objects are timing nodes, the minimum delay applies only to the path between the two nodes. When an object is a clock, the minimum delay applies to all paths where the source node (for -from) or destination node (for -to) is clocked by the clock.

You can apply the set_min_delay command exception to an output port that does not use a set_output_delay constraint. In this case, the setup summary and hold summary report the slack for these paths. Because there is no clock associated with the output port, no clock is reported for these paths, and the Clock column is empty. In this case, you cannot report timing for these paths.

Note: To report timing using clock filters for output paths with the set_min_delay command, you must use the set_output_delay command for the output port with a value of 0. You can use an existing clock from the design or a virtual clock as the clock reference in the set_output_delay command.

Maximum Delay

You can use the set_max_delay command to specify an absolute maximum delay for a given path. The following list shows the set_max_delay command, including the available options:

set_max_delay
     [-from <from list>]
     [-to <to list>]
     [-thru <thru list>]
     <delay value>

Table 2 describes the options for the set_max_delay command.

Table 2 Options Description for set_max_delay Command

Option Description
-from <from list> The <from list> is a collection or list of objects in the design. The <from list> acts as the start point of the path.
-to <to list> The <to list> is a collection or list of objects in the design. The <to list> acts as the end point of the path
-thru <thru list> The <thru list> is a collection or list of objects in the design. The <thru list> acts as the thru point of the path.
<delay value> Specifies the delay value.

If the source or destination node is clocked, then the clock paths are taken into account, allowing more or less delay on the data path. If the source or destination node has an input or output delay, that delay is also included in the maximum delay check.

When the objects are timing nodes, the maximum delay only applies to the path between the two nodes. When an object is a clock, the maximum delay applies to all paths where the source node (for -from) or destination node (for -to) is clocked by the clock.

You can apply the set_max_delay command exception to an output port that does not use a set_output_delay constraint. In this case, the setup summary and hold summary report the slack for these paths. Because there is no clock associated with the output port, no clock is reported for these paths, and the Clock column is empty. In this case, you cannot report timing for these paths.

Note: To report timing using clock filters for output paths with the set_max_delay command, you must use the set_output_delay command for the output port with a value of 0. You can use an existing clock from the design or a virtual clock as the clock reference in the set_output_delay command.