Intel® Agilex FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your Intel® FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

Intel® Agilex™ FPGA Developer Center Intel® Stratix® 10 Developer Center Intel® Arria® 10 Developer Center Intel Cyclone® 10 Developer Center Intel® Max® 10 Developer Center

1. Device Information

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Intel® Agilex™ FPGAs and SoCs Advanced Information Brief: (Device Overview)

Intel Agilex Device Data Sheet

Intel Agilex Device Family Pin Connection Guidelines

Intel Agilex Clocking and PLL User Guide

Intel Agilex Configuration User Guide

Intel Agilex General-purpose I/O and LVDS SERDES User Guide

Intel Agilex Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

Intel Agilex JTAG Boundary-Scan Testing User Guide

Intel Agilex Logic Array Blocks and Adaptive Logic Modules User Guide

Intel Agilex Power Management User Guide

Intel Agilex SEU Mitigation User Guide

Intel Agilex Embedded Memory User Guide

E-Tile Transceiver PHY User Guide

Intel Agilex Variable Precision DSP Blocks User Guide

AN 886: Intel Agilex SoC Device Design Guidelines
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Training and Videos

Intel Agilex FPGA and SoC Family

Introduction to First Shipping Intel Agilex FPGA
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Development Kits

Intel Agilex F-Series FPGA Development Kit User Guide

Intel Agilex F-Series Transceiver-SoC Development Kit User Guide
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2. Interface Protocol

Documentation

User Guides
External Memory Interface

External Memory Interfaces Intel Agilex FPGA IP User Guide

External Memory Interfaces Intel Agilex FPGA IP Design Example User Guide

PHY Lite for Parallel Interfaces Intel FPGA IP User Guide

External Memory Interfaces Support Centre
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User Guides / Application Notes
Ethernet

E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel FPGA IPs

Low Latency 100G Ethernet Intel FPGA IP Core User Guide: For Intel® Stratix 10 and Intel Agilex Devices

Low Latency E-Tile 40G Ethernet Intel FPGA IP User Guide

Ethernet Toolkit User Guide

Triple-Speed Ethernet Intel FPGA IP User Guide

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
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User Guides
PCI Express*

Intel FPGA P-Tile Avalon Memory-mapped IP for PCI Express User Guide

Intel FPGA P-Tile Avalon Streaming IP for PCI Express User Guide

Intel Agilex Device Configuration via Protocol (CvP) Implementation User Guide

Scalable Switch Intel FPGA IP for PCI Express User Guide
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User Guides / Application Notes
Other Serial IP

Interlaken (2nd Generation) Intel FPGA IP User Guide

JESD204B Intel FPGA IP User Guide

JESD204C Intel FPGA IP User Guide

Serial Lite IV Intel FPGA IP User Guide

AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex FPGA E-Tile JESD204C RX IP
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User Guides
Transceiver PHY

E-Tile Transceiver PHY User Guide
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User Guides
Embedded

Intel Agilex Hard Processor System Technical Reference Manual

Intel Agilex Hard Processor System Remote System Update User Guide

AN 886: Intel Agilex SoC Device Design Guidelines
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Design Example User Guides
Ethernet

E-tile Hard IP Intel Agilex Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

Low Latency 100G Ethernet Intel Agilex FPGA IP Design Example User Guide

Low Latency E-Tile 40G Ethernet Intel FPGA IP Design Example User Guide

Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Agilex Devices
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Design Examples User Guides
PCI Express*

Intel Agilex P-tile CvP Example Design for Initialization mode

Intel FPGA P-tile Avalon Memory-mapped IP for PCI Express Design Example User Guide

Intel FPGA P-Tile Avalon Streaming IP for PCI Express Design Example User Guide
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Design Example User Guides
Other Serial IP

Interlaken (2nd Generation) Intel Agilex FPGA IP Design Example User Guide

JESD204B Intel Agilex FPGA IP Design Example User Guide

JESD204C Intel Agilex FPGA IP Design Example User Guide

Serial Lite IV Intel Agilex FPGA IP Design Example User Guide
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Training Videos
External Memory Interface

Guide For New External Memory Interface (EMIF) spec estimator

Introduction to Memory Interfaces in Intel Agilex Devices

Integration of Memory Interfaces in Intel Agilex Devices

Verifying Memory Interfaces in Intel Agilex Devices

On-Chip Debugging of Memory Interfaces in Intel Agilex Devices
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3. Design Planning

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Intel® Quartus® Prime Pro Edition User Guide: Getting Started

Intel Quartus Prime Pro Edition User Guide: Platform Designer

Intel Quartus Prime Pro Edition User Guide: Design Recommendations

Intel Quartus Prime Pro Edition User Guide: Block-Based Design

Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration

AN 886: Intel Agilex SoC Device Design Guidelines
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Training and Videos

Manage device I/Os with the Pin Planner tool in the Quartus II software

Integration of Memory Interfaces in Intel Agilex Devices (Part 1)

Integration of Memory Interfaces in Intel Agilex Devices (Part 2)

Integration of Memory Interfaces in Intel Agilex Devices (Part 3)

Integration of Memory Interfaces in Intel Agilex Devices (Part 4)
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Developement Kits
Intel Agilex F-Series FPGA Development Kit
Intel Agilex Transceiver-SoC Development Kit
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4. Design Entry

Documentation

The Intel Quartus Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use examples available below or built-in templates to get started.

  • Verilog
  • VHDL

The Intel Quartus Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these templates, refer to the "Using Provided HDL Templates" section of the Intel Quartus Prime Pro Handbook.

The Intel Quartus Prime design software also comes with Intel® High Level Synthesis Compiler which synthesizes a C++ function into an RTL implementation that is optimized for Intel FPGA products

User Guides / Device Overview / Device Datasheet / White Paper
Design Recommendations User Guide: Intel Quartus Prime Pro Edition
Intel High Level Synthesis Compiler Getting Started Guide
Intel High Level Synthesis Compiler User Guide
Scripting User Guide: Intel Quartus Prime Pro Edition
Advanced Synthesis Cookbook
Intel High Level Synthesis Compiler Best Practices Guide
Intel High Level Synthesis Compiler Reference Manual
Intel High Level Synthesis Compiler Release Notes
Applying the Benefits of Network on a Chip Architecture to FPGA System Design
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Design Examples
Platform Designer Design Examples
Platform Designer Tutorial Design Example (.zip)
VHDL Examples
Verilog Examples
Quartus® Design Examples
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Training and Videos

Using the Quartus Prime Software: An Introduction

Introduction to Verilog HDL

Verilog HDL Basics

Advanced Verilog HDL Design Techniques

SystemVerilog with the Quartus II Software

Introduction to VHDL

VHDL Basics

Advanced VHDL Design Techniques

Introduction to Platform Designer

Platform Designer in the Intel® Quartus Prime Pro Edition Software

Creating a System Design with Platform Designer: Getting Started

Using Spectra-Q Synthesis in the Quartus Prime Software

Good High-Speed Design Practices
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Software Downloads
Download Center for all versions of the Intel Quartus Prime software
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5. Simulation and Verification

Documentation

User Guides / Application Notes

Intel Quartus Prime Pro Edition User Guide: Third-party Simulation

Avalon® Verification IP Suite User Guide

Mentor Verification IP Intel FPGA Edition AMBA* AXI3 and AXI4 User Guide

Intel FPGA Software Installation and Licensing

AN 351: Simulating Nios® II Processor Designs
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Design Examples

Avalon® Verification IP Suite Design Example
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Training and Videos

Advanced System Design Using Qsys: Component & System Simulation

Verifying Memory Interfaces in Intel Agilex Devices

Avalon Verification Suite

How to Set Up RTL Simulations in Quartus, Qsys and Third Party Simulators
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6. Implementation and Optimization

Documentation

User Guides / Application Notes

Intel Quartus Prime Pro Edition User Guide: Design Recommendations

Intel Quartus Prime Pro Edition User Guide: Design Compilation

Intel Quartus Prime Pro Edition User Guide: Design Optimization

Intel Quartus Prime Pro Edition User Guide: Third-party Synthesis

Intel Quartus Prime Pro Edition User Guide: Power Analysis and Optimization

Intel Agilex Variable Precision DSP Blocks User Guide

Intel Agilex Logic Array Blocks and Adaptive Logic Modules User Guide

Intel Hyperflex Architecture High-Performance Design Handbook

AN 886: Intel Agilex SoC Device Design Guidelines
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Training and Videos

Introduction to Hyper-Optimization

Intel Quartus Prime Software Hyper-Aware Design Flow

Performance Optimization with Intel® Hyperflex™ Architecture

Advanced Optimization with Intel Hyperflex Architecture

Intel Hyperflex Architecture Overview for Intel Agilex™ Devices

Introduction to Hyper-Pipelining

Eliminating Barriers to Hyper-Retiming

Intel Hyperflex FPGA Architecture Design: Analyzing Critical Chains

Hyper-Optimization Techniques 2: Pre-Computation

Hyper-Optimization Techniques 3: Shannon’s Decomposition

The Intel HyperFlex FPGA Optimization Workshop

Performance Optimization with Intel Hyperflex Architecture

Intel Hyperflex Architecture Overview for Intel Agilex Devices
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7. Timing Analysis

Documentation

User Guides / Application Notes

Timing Analyzer Quick-Start Tutorial Intel Quartus Prime Pro Edition

Intel Quartus Prime Pro Edition User Guide: Timing Analyzer

Intel Quartus Prime Pro Edition User Guide: Design Constraints

Intel Quartus Prime Pro Edition User Guide: Scripting

SDC and TimeQuest API Reference Manual

Intel Quartus Prime Timing Analyzer Cookbook

AN 775: Generating Initial I/O Timing Data: for Intel FPGAs

AN 471: High-Performance FPGA PLL Analysis with TimeQuest

AN 433: Constraining and Analyzing Source-Synchronous Interfaces

AN 775: I/O Timing Information Generation Guidelines
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Design Examples

Timing Analyzer Design Examples
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Training and Videos

Getting Started with the TimeQuest Timing Analyzer

TimeQuest Timing Analyzer: Introduction to Timing Analysis

Advanced Timing Analysis with TimeQuest

TimeQuest Timing Analyzer: Quartus Prime Integration & Reporting

TimeQuest Timing Analyzer: Required SDC Constraints

TimeQuest Timing Analyzer: TimeQuest GUI

The Quartus Prime Software Design Series: Timing Analysis
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8. On-Chip Debug

Documentation

User Guides / Application Notes

Intel Quartus Prime Pro Edition User Guide: Programmer

Intel Quartus Prime Pro Edition User Guide: Debug Tools

Analyzing and Debugging Designs with System Console

Intel FPGA USB Download Cable User Guide

Intel FPGA Download Cable II User Guide

Design Debugging Using In-System Sources and Probes

Intel FPGA Virtual JTAG (Intel FPGA_virtual_jtag) IP Core User Guide

BSDL Support

AN 827: Unified Tool for Generating Programming Files

AN 446: Debugging Nios II Systems with the SignalTap II Logic Analyzer

AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems, Design files

AN 543: Debugging Nios II Software Using the Lauterbach Debugger
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Training and Videos

Advanced System Design Using Qsys: System Verification with System Console

Debugging & Communicating with an FPGA Using the Virtual JTAG Megafunction

Debugging JTAG Chain Integrity

SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals

The Quartus® Software Debug Tools

Setting Up and Debugging Quartus Floating Licenses

JTAG Chain Debugger Tool

U-Boot Console and FDT Debug

Quartus In Systems Sources and Probes Debug Flow

Quartus II Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs

Debugging Techniques for Qsys and Nios Based Bare Metal Systems

Understanding and Utilizing USB Blaster and JTAG to Configure Intel FPGAs

On-Chip Debugging of Memory Interfaces in Intel Agilex Devices

Debugging with the Ethernet Toolkit

Intel® Agilex FPGA Configuration

Introduction to Intel® Stratix® 10 Secure Device Manager (SDM) Debug Toolkits
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Software Downloads

Intel Advanced Link Analyzer

Intel Quartus Prime Pro Edition

Quartus Prime Pro Edition Programmer and Tools
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