JESD204B Intel® FPGA IP Core – Support Center

Device Family PMA Speed Grade FPGA Fabric Speed Grade

Data Rate

Enable Hard PCS (Gbps)                 Enable Soft PCS (Gbps) 1

Link Clock fMAX (MHz)
Intel® Agilex™ (E-Tile)

2

3

-2

-2

-3

 

Not supported

Not supported

Not supported

 

2.0 to 17.4

2.0 to 17.4

2.0 to 16.0

 

data_rate/40

data_rate/40

data_rate/40

 

Intel® Stratix® 10 (L-Tile and H-Tile)

1

 

2

 

3

1

2

1

2

1

2

3

2.0 to 12.0

2.0 to 12.0

2.0 to 9.83

2.0 to 9.83

2.0 to 9.83

2.0 to 9.83

2.0 to 9.83

2.0 to 16.02

2.0 to 14.0

2.0 to 16.02

2.0 to 14.0

2.0 to 16.02

2.0 to 14.0

2.0 to 13.0

data_rate/40

data_rate/40

data_rate/40

data_rate/40

data_rate/40

data_rate/40

data_rate/40

Intel® Stratix® 10 (E-Tile)

 

 

Not supported 

Not supported

Not supported

Not supported 

Not supported 

2.0 to 16.02

2.0 to 14.0

2.0 to 16.02

2.0 to 14.0

2.0 to 13.0

data_rate/40

data_rate/40

data_rate/40

data_rate/40

data_rate/40
Intel® Arria® 10

1

2

 

3

 

4

1

1

2

1

2

3

2.0 to 12.0

2.0 to 12.0

2.0 to 9.83

2.0 to 12.0

2.0 to 9.83

2.0 to 8.83

2.0 to 15.0 2 3

2.0 to 15.0 2 3

2.0 to 15.0 2 3

2.0 to 14.2 2 4

2.0 to 14.2 2 5

2.0 to 12.56

data rate/40c

data rate/40

data rate/40

data rate/40

data rate/40

data rate/40
Intel® Cyclone® 10 GX <Any supported speed grade> <Any supported speed grade> 2.0 to 6.25 2.0 to 6.25 data rate/40

Title

Type

Description

JESD204B MegaCore IP Overview

Online

This online course provides a broad overview of the JESD204B Intel FPGA IP core. For better understanding of all the terms and concepts used in the course, we begin with a discussion of the relevant portions of the JESD204B interface specification, and followed by a presentation of some of the important features of the JESD204B Intel FPGA IP core. Finally, a data flow of the system is used to describe the functional details of the core.

Title

Description

Arria® 10 interface to ADI 9144 using JESD204B IP

Learn about the interoperability of JESD204B Intel FPGA IP core on the Intel® Arria® 10 FPGA with the AD9144 converter from Analog Devices Inc. (ADI). 

How to interoperate ADI AD9680 with Intel® FPGA JESD204B IP Core on Stratix® V FPGA

Get a step-by-step guide on how to set up the hardware, configure the analog-to-digital converter, and configure the JESD204B Intel FPGA IP core.

How to interoperate ADI AD9680 with Intel® FPGA JESD204B IP on Stratix V

Get a step-by-step guide on how to set up the hardware, configure the analog-to-digital converter, and configure the JESD204B Intel FPGA IP core.

How to interoperate TI DAC37J84 with Intel® FPGA JESD204B MegaCore on Stratix V FPGA

Learn about the interoperability of JESD204B Intel FPGA IP core on the Stratix® V FPGA with the DAC37J84 converter from Texas Instruments.

JESD204B Intel FPGA IP Quick Start Video

Learn about JESD204B standard and the JESD204B Intel FPGA IP solution. Find out how you can easily create a design example that works on hardware.

JESD204B Intel FPGA IP Demonstration

Learn about the interoperability of JESD204B Intel FPGA IP core on the Arria V FPGA with the DAC37J84 converter from Texas Instruments.

JESD204B Intel FPGA IP Quick Start Video

Learn about JESD204B standard and the JESD204B Intel FPGA IP solution. Find out how you can easily create a design example that works on hardware.