Intel® Quartus® Prime Design Software - Support Center

Course Name Type Duration Course Number
Using the Quartus® Prime Software: An Introduction Online 81 Minutes ODSW1100
The Quartus® Prime Software: Foundation (Standard Edition) Online 8 Hours ODSW1110
The Quartus® Prime Software: Foundation (Pro Edition) Online 8 Hours ODSW1110PRO
Intel® Quartus® Prime Software: Pro Edition Features for High-End Designs Instructor-Led / Virtual Class 8 Hours IPRO
The Intel® Quartus® Prime Software: Foundation Instructor-Led / Virtual Class 8 Hours IDSW110
Tool I/O Planning Task How to Access
Interface Planner Plan interfaces and device periphery Tools > Interface Planner
Pin Planner Edit, validate, or export pin assignments Assignments > Pin Planner
Course Type Duration Course Number
Fast & Easy I/O System Design with BluePrint Free, Online 40 minutes OBLUEINTRO
Course Type Duration Course Number
Introduction to Verilog HDL 8 Hours Instructor-Led IHDL120
Introduction to VHDL 8 Hours Instructor-Led IHDL110
Verilog HDL Basics 50 Minutes Online, Free OHDL1120
VHDL Basics 92 Minutes Online, Free OHDL1110
Advanced Verilog HDL Design Techniques 8 Hours Instructor-Led IHDL230
Advanced VHDL Design Techniques 8 Hours Instructor-Led IHDL240
SystemVerilog with the Quartus® II Software 38 Minutes Online, Free OHDL1125
Resource Description
Good High-Speed Design Practices (ODSWTC01) Free, online training
Recommended HDL Coding Styles A section in the Intel® Quartus® Prime Pro Edition User Guide
Recommended Design Practices A section in the Intel® Quartus® Prime Pro Edition User Guide
Advanced Synthesis Cookbook with design examples (cookbook.zip) PDF with design examples
Resource Description
Intel® FPGA IP Portfolio Overview of Intel® FPGA IP portfolio
Introduction to Intel® FPGA IP Cores How the IP catalog and parameter editor manage IP cores in the Intel® Quartus® Prime software
Intel® FPGA IP Finder A comprehensive list of Intel® FPGA IP cores
Resource Description
Creating a System with Platform Designer Basics of using the Platform Designer
Creating Platform Designer Components How to integrate intellectual property (IP) components for use in the Platform Designer
Platform Designer Interconnect Details on the memory-mapped and streaming interfaces available in the Avalon® and AMBA* AXI* interconnection standards
Optimizing Platform Designer System Performance Optimizing pipelines and dealing with bus arbitration in a Platform Designer system
Component Interface Tcl Reference Application programming interface (API) reference for integrating IP into the Platform Designer system
Platform Designer System Design Components Description of the interconnection components available in the Platform Designer
Course Duration Type Course Number
Creating a System Design with Qsys 37 Minutes Free, Online OQSYSCREATE
Introduction to Qsys 26 Minutes Free, Online OQSYS1000
Introduction to the Platform Designer System Integration Tool 8 Hours Instructor-Led IQSYS101
System Design with Qsys Pro 42 Minutes Free, Online OQSYSPRO
Advanced System Design Using Qsys: Component & System Simulation 28 Minutes Free, Online OAQSYSSIM
Advanced System Design Using Qsys: Qsys System Optimization 32 Minutes Free, Online OAQSYSOPT
Advanced System Design Using Qsys: System Verification with System Console 25 Minutes Free, Online OAQSYSSYSCON
Advanced System Design Using Qsys: Utilizing Hierarchy in Qsys Designs 22 Minutes Free, Online OAQSYSHIER
Advanced Qsys System Integration Tool Methodologies 8 Hours Instructor-Led IQSYS102
Custom IP Development Using Avalon® and AXI* Interfaces 113 Minutes Free, Online OQSYS3000
Resources Description
Platform Designer - Design Example Downloadable design example of a memory tester implemented in the Platform Designer.
AXI* Memory Design Example AMBA* AXI*-3 Agent interface on a simple Verilog custom memory component.
BFM Simulation Example: HPS AXI* Bridge Interface to FPGA Core A hard processor system (HPS) interface to the FPGA AXI* bridge (h2f).
Avalon® Verification IP Suite User Guide (PDF) Bus functional models (BFMs) to verify IP cores using Avalon® interfaces.
Design files (.zip)
Mentor Graphics* AXI* Verification IP Suite (PDF) BFMs to verify IP cores using AMBA* AXI* interfaces.
Resource Description
Comparing IP Integration Approaches for FPGA Implementation Discusses the interconnection challenges in complex FPGA devices.
Applying the Benefits of Network on a Chip Architecture to FPGA System Design  Describes the advantages of network on a chip (NoC) architectures in Intel® FPGA system design.
Resource Description
Using NativeLink Simulation A chapter in the Intel Quartus Prime Standard Edition User Guide: Third-party Simulation
How to Set Up NativeLink Simulation A short video that demonstrates how to set up NativeLink for a simple design
Resource Type Description
Simulating Intel® FPGA Designs (Intel® Quartus® Prime Pro Edition) A section in Intel® Quartus® Prime Pro Edition User Guide Main documentation for the Intel® Quartus® Prime Pro Edition software
Simulating Intel® FPGA Designs (Intel® Quartus® Prime Standard Edition) Intel® Quartus® Prime Standard Edition Handbook Main documentation for the Intel® Quartus® Prime Standard Edition software
Generating a Testbench with the Intel® FPGA-ModelSim* Simulation Tool Demonstration Video  
Simulating a Nios® II Processor Design Demonstration Video  
How to Simulate Active Serial Memory Interface Block Demonstration Video  
Generating PHYLite Example Design Simulation in ModelSim* in 16.1 with Arria® 10 Demonstration Video  
How to Simulate Cyclone® V 8b10b IP Byte Ordering Demonstration Video  
Simulating Arria® 10 RLDRAM3 Using the Vendor Memory Model Demonstration Video  
Ping Pong PHY DDR3 Simulation Demonstration Video  
Simulation of SoC HPS DDR3 Core Demonstration Video  
Advanced System Design Using Qsys: Component & System Simulation Online, Free Training 28-minute online course (OAQSYSSIM)
Simulating Designs with 3rd Party EDA Simulators (Legacy Course) Online, Free Training 35-minute online course (ODSW1122)
Title Description
Quartus Prime Integrated Synthesis The Intel® Quartus® Prime software integrated synthesis tool supports the synthesis of VHDL, Verilog, SystemVerilog, and legacy Intel® FPGA-specific design entry languages. 
Synplify Support The Intel® Quartus® Prime software tool flow also supports the Synplicity Synplify and Synplify Pro logic synthesizers. 
Mentor Graphics* Precision RTL Support The Intel® Quartus® Prime software tool flow also supports the Mentor Graphics* Precision RTL Synthesizer. 
Title Description
Using the Quartus® Prime Software: An Introduction (ODSW1100)

Become familiar with the basic Quartus® Prime software design environment. You will learn about a basic FPGA design flow and how to use the Quartus® Prime software in the flow.

This is a 1.5-hour online course.

The Quartus® Prime Software Design Series: Foundation (Standard) (ODSW1110)

Learn to use the Quartus® Prime software to develop an FPGA or CPLD design from initial design to device programming.

This is a 3.5-hour online course.

The Quartus® Prime Software Design Series: Foundation (IDSW110)

Create a project, enter design files, compile, and configure your device to see the design working in-system. Enter timing constraints and analyze a design using the Timing Analyzer. Discover how the software interfaces with common EDA tools used for synthesis and simulation.

This is an 8-hour instructor-led course.

Document Description
HLS Getting Started Guide Shows how to initialize your high-level synthesis compiler environment. Also includes design examples and tutorials to demonstrate ways to effectively use the compiler.
HLS User Guide Provides instructions on synthesizing, verifying, and simulating IP cores for Intel® FPGA products.
HLS Reference Manual Provides information about the high-level synthesis (HLS) component design flow, including command options and other programming elements you can use in your component code.
HLS Best Practices Guide Offers tips and guidance on how to optimize your component design using information provided by the HLS compiler.
Fitter Stage Incremental Optimization
Plan After this stage, you can run post-plan timing analysis to verify timing constraints and validate cross-clock timing windows. View the placement and periphery properties and perform clock planning for Intel® Arria® 10 FPGA and Intel® Cyclone® 10 FPGA designs.
Early Place After this stage, the Chip Planner can display an initial high-level placement of design elements. Use this information to guide your floorplanning decisions. For Intel® Stratix® 10 FPGA designs, you can also do early clock planning after running this stage.
Place After this stage, validate the resource and logic utilization in the Compilation Reports and review the placement of design elements in the Chip Planner.
Route After this stage, perform detailed setup and hold timing closure in the Timing Analyzer and view routing congestions via the Chip Planner.
Retime After this stage, review the Retiming results in the Fitter report and correct any restrictions limiting further retiming optimization.
Course Duration Type Course Number
The Intel Quartus Prime Software Design Series: Timing Analysis 8 Hours Intructor-Led IDSW120
Advanced Timing Analysis with TimeQuest 8 Hours Instructor-Led IDSW125
Timing Analyzer: Introduction to Timing Analysis 15 Minutes Online, Free ODSW1115
Timing Analyzer: Timing Analyzer GUI 31 Minutes Online, Free ODSW1116
Timing Analyzer: Intel Quartus Prime Integration & Reporting 25 Minutes Online, Free ODSW1117
Timing Analyzer: Required SDC Constraints 34 Minutes Online, Free ODSW1118
Timing Closure Using TimeQuest Custom Reporting 24 Minutes Online, Free OTIM1100
Course Duration Type Course Number
Incremental Block-Based Compilation in the Intel® Quartus® Prime Pro Software: Timing Closure & Tips 22 Minutes Online, Free OIBBC102
Design Evaluation for Timing Closure 55 Minutes Online, Free ODSWTC02
Best HDL Design Practices for Timing Closure 61 Minutes Online, Free OHDL1130
Timing Closure Using TimeQuest Custom Reporting 24 Minutes Online, Free OTIM1100
Timing Closure with the Quartus® II Software 8 Hours Instructor-Led IDSW145
Title Description
Area and Timing Optimization This user guide section explains how to reduce resource usage, reduce compilation times, and improve timing performance when designing for Intel® devices.
Analyzing and Optimizing the Design Floorplan This user guide section describes how to use the Chip Planner to analyze and optimize the floorplan for your designs. This chapter also explains how to use Logic Lock Region to control the placement.
Engineering Change Management with the Chip Planner This user guide section describes how to use the Chip Planner to implement engineering change orders (ECOs) for supported devices.
Netlist Optimizations and Physical Synthesis This user guide section explains how the netlist optimizations and physical synthesis in Intel® Quartus® Prime software can modify your design’s netlist and help improve the quality of your results.
Incremental Compilation Resource Center This resource center web page shows how you can use incremental compilation to reduce compilation times and preserve results during optimization.
Course Duration Type Course Number
Using Intel® Quartus® Prime Pro Software: Chip Planner 29 Minutes Online, Free OPROCHIPPLAN
Using Design Space Explorer 21 Minutes Online, Free ODSE
Timing Closure Using Timequest Custom Reporting 24 Minutes Online, Free OTIM1100
Best HDL Design Practices for Timing Closure 1-hour Online, Free OHDL1130
Resource Description
Optimizing the Design Netlist A section in the Intel® Quartus® Prime Standard Edition User Guide: Design Optimization, covering the use of the Netlist Viewers.
Resource Type Description
Analyzing and Optimizing the Design Floorplan Design Optimization User Guide: Intel® Quartus® Prime Pro Edition Chapter Primary documentation for Design Floorplan and Chip Planner
Chip Planner Instructional Video (Part 1 of 2) E2E Video Chip Planner tutorial: Cross Reference Timing Paths, Fan-in, Fan-out, Routing Delays, and Clock Regions
Chip Planner Instructional Video (Part 2 of 2) E2E Video Chip Planner tutorial: Routing Utilization, Design Element Search, and Logic Lock Regions
Making ECO changes using Intel FPGA Quartus Chip Planner and Resource Property Editor (Part 1 of 3) E2E Video Making late, small engineering change order (ECO) changes using the Chip Planner
Making ECO changes using Intel FPGA Quartus Chip Planner and Resource Property Editor (Part 2 of 3) E2E Video Making late, small ECO changes using the Chip Planner
Making ECO changes using Intel FPGA Quartus Chip Planner and Resource Property Editor (Part 3 of 3) E2E Video Making late, small ECO changes using the Chip Planner
How to trace the local routing of CDR recovered clock from transceiver channel to I/O pin using the Timing Analyzer and Chip Planner E2E Video An example of how to use the Chip Planner with the Timing Analyzer
Resource Description
Optimizing with Design Space Explorer II Getting Started User Guide: Intel® Quartus® Prime Pro Edition
Design Space Explorer (DSE) Design Example An example of a design space exploration
Using Design Space Explorer (ODSE) Free online training, 21 minutes
Resource Description
Intel® FPGA Virtual JTAG (Intel® FPGA_virtual_jtag) IP Core User Guide (PDF) The Intel® FPGA_virtual_jtag Intel® FPGA IP communicates via a JTAG port, allowing you to develop custom debugging solutions.

AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems (PDF)

Design files (.zip)

Using SignalTap to monitor signals located inside a system module generated by the Platform Designer.
AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer (PDF) This application note examines the use of the Nios® II plug-in within the Signal Tap logic analyzer and presents the capabilities, configuration options, and use-modes for the plug-in.
AN 799: Quick Debugging of Intel® Arria® 10 Designs Using Signal Probe and Rapid Recompile Access internal signals with minimal impact on your design.
Resource Description
Running Rapid Recompile Rapid Recompile section in volume 2 of the Intel® Quartus® Prime Pro Edition Handbook
AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile (PDF) An application note showing how Rapid Recompile reduces the compile time for small changes
Resource Description
Quartus® II Scripting Reference Manual Covers both Quartus® software command-line executables and Tcl packages and commands from within a Quartus® software shell
Quartus® Prime Standard Edition Settings File Reference Manual Covers parameter settings found in the Quartus® software Settings File (.qsf).
Command Line Scripting A section of the Intel Quartus Prime Standard Edition User Guide.
Quartus® II Tcl Examples A web page with several useful Tcl script examples.
Command Line Scripting (ODSW1197) Online training presenting the command line scripting capabilities in the Intel® Quartus® software (30 min).
Introduction to Tcl (ODSW1180) An Introduction to the Tcl scripting syntax.
Quartus® II Software Tcl Scripting (ODSW1190) Tcl Scripting capabilities in the Quartus® II software.