EDA Partners: FPGA EDA Systems

EDA Partners

Our EDA ecosystem ensures that you have a complete design solution in designing, verifying, and integrating Intel® FPGAs into your systems.

System-Level Design

EDA Vendor

Product Name

Design Solution

Altium

Altium Designer

High-level design tool

Agnisys Technology Pvt Ltd

IDesignSpec

Register map management

Bluespec

Bluespec Compiler

High-level synthesis

Cadence Design Systems, Inc.

Stratus High-Level Synthesis

High-level synthesis

Duolog Technologies

Socrates

Register map management

Impulse Accelerated Technologies

ImpulseC CoDeveloper

High-level synthesis and simulation

NEC

CyberWorkBench

High-level synthesis

PDTi

SpectaReg

Register map management

Poseidon Design Systems

Triton Tuner

System-level simulation

Triton Builder

High-level synthesis

SynaptiCAD

TestBencher Pro

High-level design tool

Design Creation

EDA Vendor

Product Name

Design Solution

Mentor Graphics®

HDL Designer

Project management, design entry, and analysis tool

Sigasi

Sigasi HDT

Design entry, code comprehension, project management, and collaboration

Synthesis

EDA Vendor

Product Name

Design Solution

Mentor Graphics

Precision RTL

Logic synthesis

Precision RTL Plus

Advanced logic synthesis

Precision Physical

Timing closure tool

Synopsys

Synplify Pro

Logic synthesis tool

Synplify Premier

Timing closure tool

Simulation

EDA Vendor

Product Name

Design Solution

Aldec, Inc.

Active-HDL

Simulation

Riviera-PRO

Simulation

Cadence Design Systems, Inc.

Incisive Enterprise Simulator

Simulation

Mentor Graphics

ModelSim®

Simulation

Questa Advanced Simulator

Simulation

Metrics Design Automation

Metrics Cloud Simulator
(SaaS Cloud Computing Environment for simulation)

Simulation

Symphony EDA

VHDL Simili

Simulation

SynaptiCAD

VeriLogger Extreme

Simulation

Synopsys

VCS

Simulation

Verification

EDA Vendor

Product Name

Design Solution

Aldec, Inc.

ALINT-PRO

Design Rule Checking and Clock Domain Crossing (CDC) Verification

Blue Pearl

Analyze RTL

RTL checker

Create Timing Constraints

Constraints generator

Clock Domain Crossing (CDC) Verification

Clock Domain Crossing (CDC)

Cadence Design Systems, Inc.

Encounter Conformal Equivalence Checker

Formal verification

EMA Design Automation

TimingDesigner

Timing verification

FishTail

Focus

Constraints generator

Confirm

Timing-exception verification

ReConfirm

Timing-exception validation

Mentor Graphics

FormalPro

Equivalence checking

Questa Formal Verification

Functional verification

Questa Clock-Domain Crossing Verification

Clock domain crossing verification

Real Intent

Meridian CDC

Clock domain crossing verification

SynaptiCAD

TestBencher Pro

Testbench generator

WaveFormer Pro

Timing verification

Synopsys

SpyGlass for FPGA

RTL analysis for FPGA designs

SpyGlass Lint

Lint checks

SpyGlass CDC

Clock domain crossing (CDC) verification

VC Formal

Functional property verification

Formality

Logic equivalence checking

Temento Systems

Dialite – Platform Edition

In-system verification and integrated RTL debug

AMBA Bus Verification

In-system verification

TransEDA

VN-Spec

Specification checker

VN-Check

RTL checker

VN-Cover

Finite state machine (FSM) coverage tool

Coverability Analysis

Code coverage tool for simulation and testbench generation

Assertain-HDL

RTL checker for simulation coverage

Assertain-ABV

RTL checker for functional verification coverage

Board-Level Design

EDA Vendor

Product Name

Design Solution

Agilent Technologies

Advanced Design System (ADS)

Signal integrity (SI) analysis

Altium

Altium Designer

PCB board schematics and layout
SI analysis

Cadence Design Systems, Inc.

Allegro FPGA System Planner

FPGA I/O planning

OrCAD FPGA System Planner

FPGA I/O planning

Allegro PCB SI

SI analysis

OrCAD Signal Explorer

SI analysis

Allegro Design Authoring
Allegro Design Entry Capture / Capture CIS

PCB board schematics

Cadence OrCAD Capture and Capture CIS

PCB board schematics

Allegro PCB Designer

PCB board layout

OrCAD PCB Designer

PCB board layout

Mentor Graphics

I/O Designer

FPGA I/O planning

HyperLynx Signal Integrity (SI)

SI analysis

DxDesigner

PCB board schematics

PADS

PCB board schematics and layout

Expedition Enterprise

PCB board layout

Board Station

PCB board layout

Signal Integrity Software, Inc. (SiSoft)

Quantum-SI

SI analysis

Synopsys

HSPICE

SI analysis

Zuken

CR-5000

PCB board schematics and layout

ASIC Prototyping

EDA Vendor

Product Name

Design Solution

Synopsys

Certify

Multi-chip partitioning system

Design Optimization

EDA Vendor Product Name Design Solution
Plunify Intime Design Optimization Software

All EDA Partners

ACCESS Program Partner

System- Level Design

Design Creation

Synthesis

Simulation

Verification

Board-Level Design

ASIC Prototyping

Design Optimization

Aldec, Inc.

 

 

 

 

 

 

Agilent Technologies

 

 

 

 

 

 

 

Agnisys Technology Pvt Ltd

 

 

 

 

 

 

 

Altium

 

 

 

 

 

 

Atrenta

 

 

 

 

 

 

 

Blue Pearl

 

 

 

 

 

 

 

Bluespec

 

 

 

 

 

 

 

Cadence Design Systems,Inc.

 

 

 

 

Duolog Technologies

 

 

 

 

 

 

 

EMA Design Automation

 

 

 

 

 

 

 

FishTail

 

 

 

 

 

 

 

Impulse Accelerated
Technologies

 

 

 

 

 

 

 

Mentor Graphics

 

NEC

 

 

 

 

 

 

 

PDTi

 

 

 

 

 

 

 

Plunify

 

 

 

 

 

 

 

Poseidon Design Systems

 

 

 

 

 

 

 

Real Intent

 

 

 

 

 

 

 

Sigasi

 

 

 

 

 

 

 

Signal Integrity Software, Inc. (SiSoft)

 

 

 

 

 

 

 

Symphony EDA

 

 

 

 

 

 

 

SynaptiCAD

 

 

 

 

 

Synopsys®

 

 

Temento Systems

 

 

 

 

 

 

 

TransEDA

 

 

 

 

 

 

 

Zuken