Intel® FPGA Package and Thermal Information
Package information includes the ordering code reference, package acronym, leadframe material, lead finish (plating), JEDEC® outline reference, lead coplanarity, weight, moisture sensitivity level, and other special information. The thermal resistance information includes device pin count, package name, and resistance values.
Table 2 - Package and Thermal Technical Documentation |
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Application Notes and White Papers |
AN752: Guidelines for Handling Intel® FPGA Wafer level chip scale package |
AN657: Thermal management and mechanical handling for Intel FPGA TCFCBGA devices |
AN659: Thermal management and mechanical handling for lidless flip chip ball-grid array |
AN 114: Designing with high-density BGA packages for Intel devices |
AN 71: Guidelines for handling J-Lead, QFP, BGA, FBGA, and lidless devices |
Challenges in manufacturing reliable lead-free and RoHS-compliant components |
Note 2 - For other devices not listed in Table 1, please see the Package Information Datasheet for Mature Devices, or visit the Intel® FPGA Device Support Resources to find more information about Mature and Legacy Device Support Collections.