PCI* Express (PCIE) IP Core Resource Center
Intel® FPGA provides extensive documentation and support for the PCI Express MegaCore function to help you quickly and easily develop and debug PCI Express (PCIe) applications.
- PCI Express
- Arria® V GZ Hard IP for PCI Express User Guide
- Arria® V Hard IP for PCI Express User Guide
- Cyclone® V Hard IP for PCI Express User Guide
- Stratix® V Hard IP for PCI Express User Guide
- IP Compiler for PCI Express User Guide (Arria® II GX and GZ, Cyclone® IV GX, and Stratix® IV GX)
- MegaCore IP Library Release Notes
- Archive of Intellectual Property Release Notes
- Low-Cost FPGA Solutions for PCI Express Implementation White Paper
- AN 431: PCI Express–to-External Memory Reference Design (Arria® GX and Stratix® II FPGAs)
- AN 443: External PHY Support in PCI Express MegaCore Functions
- AN 456: PCI Express High-Performance Reference Design (Stratix IV GX, Stratix II GX, and Arria GX FPGAs)
- AN 532: An SOPC Builder PCI Express Design with GUI Interface
Intel FPGA Knowledge Database
The Knowledge Database provides support solutions, answers to frequently asked questions, and information about known issues regarding the PCI Express MegaCore function.
See frequently viewed solutions:
- When the PCI Express hard IP block is enabled in Stratix IV GX devices, can I use all the other transceiver channels in a transceiver block?
- Can I use the PCI Express hard IP with an external PHY?
- PCI Express Compiler User Guide Version 9.0: Known Issues
- When I simulate the PCI Express (PIPE) x8 configuration in a Stratix IV GX device, why is the coreclkout  port always at logic low?
Find additional solutions on the PCI Express MegaCore function.
The following development kits are available for the PCI Express MegaCore function: