Serial Digital Interface II IP Support Center

Ensure to enable option “CRC error output” in the SDI II Intel® FPGA IP Parameter Editor for correct CRC values (not applicable for SD-SDI).

Make sure the clock signal frequency is connected to the correct onboard clock frequency. For example, if the SDI Tx PLL reflck clock signal is configured to 148.5 MHz, then use 148.5 MHz clock chip as well to connect to SDI Tx PLL refclk signal.

For serial loopback example design, customer can see all the supported video resolution in .tcl file at this directory <example design folder>\hwtest\tpg_ctrl.tcl. For parallel loopback example design, this .tcl file is not available, but customer can still access all the supported video resolution in SMPTE specification.

Make sure the clock signal frequency is connected to the correct onboard clock frequency. For example, if the SDI Tx PLL reflck clock signal is configured to 148.5 MHz, then use 148.5 MHz clock chip as well to connect to SDI Tx PLL refclk signal.

For serial loopback example design, customer can see all the supported video resolution in .tcl file at this directory <example design folder>\hwtest\tpg_ctrl.tcl. For parallel loopback example design, this .tcl file is not available, but customer can still access all the supported video resolution in SMPTE specification.