F-Tile Interlaken Intel® FPGA IP Design Example User Guide

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ID 683069
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example 1.6. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Analog Parameters Settings 2.3. Design Example Flow 2.4. Interface Signals 2.5. Register Map 2.6. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

1.5. Compiling and Configuring the Hardware Design Example

  1. Ensure the example design generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_installation_dir>/example_design.qpf>.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a .sof file is available in your specified directory. Follow these steps to program the hardware example design on the Intel Agilex® 7 device with F-tile:
    1. Connect the Development Kit to the host computer.
    2. Launch the Clock Control application, which is part of the development kit. Set new frequencies for the design example as following:
      • For NRZ mode:
        • Si5391-A (U18), OUT0: Set to the value of pll_ref_clk 2 to 156.25 MHz.
        • Si5332 (U19), OUT6: Set to the value of mgmt_clk 2 to 100 MHz.
      • For PAM4 mode:
        • Si5391-B (U45), OUT1: Set to the value of pll_ref_clk 2 to 156.25 MHz.
        • Si5332 (U19), OUT1: Set to the value of mac_pll_ref_clk 2 to 156.25 MHz.
        • Si5332 (U19), OUT6: Set to the value of mgmt_clk 2 to 100 MHz.
        • For FHT or when EFIFO is enabled:
          • Si5394 (U118), OUT3: Set to the value of systempll_ref_clk 2 per your design requirement.
    3. Click Tools > Programmer > Hardware Setup.
    4. Select a programming device. Add the Intel Agilex® 7 I-Series Transceiver-SoC Development Kit.
    5. Ensure that Mode is set to JTAG.
    6. Select the Intel Agilex® 7 I-Series device and click Add Device. The programmer displays a diagram of the connections between the devices on your board.
    7. Check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.
Related Information
2 The Clock Control GUI application cannot drive all the frequencies.
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