PHY Lite for Parallel Interfaces Intel® FPGA IP Cores Release Notes

ID 683090
Date 4/01/2024
Public
Document Table of Contents

PHY Lite for Parallel Interfaces Intel Agilex FPGA IP v20.3.0

Table 3.  v20.3.0 2020.12.14
Intel® Quartus® Prime Version Description Impact
20.4
  • Added support for dynamic reconfiguration.
  • Added design example with dynamic reconfiguration.
  • Added Pin Placement tab in the parameter editor, to allow pin placement settings for all groups and graphical support of data/strobe pin placement within sub-bank. Removed pin placement settings in each group.
  • Added support for half-rate and full-rate.
  • Added support for I/O sub-bank pin 7 in each lane to be used as data pin.
  • Added sub-bank ID to facilitate pin placement at the IP generation stage.