F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

2.2.3. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench

The simulation testbench instantiates the SR-IOV design example and a Root Port BFM to interface with the target Endpoint.

Figure 12. Block diagram for the PCIe x16 SR-IOV Design Example Simulation Testbench

The test program writes to and reads back data from the same location in the on-chip memory across 2 PFs and 32 VFs per PF. It compares the data read to the expected result. The test reports, "Simulation stopped due to successful completion" if no errors occur. The SR-IOV design example supports Gen4 x16 Endpoint.