F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

3.3.1.4. Steps to Run Simulation : Xcelium*

Working Directory

<example_design>/ pcie_ed_tb/pcie_ed_tb/sim/xcelium/

Instructions

  1. Run the following commands:

    For FASTSIM + PIPE mode:
    Note: Enable PIPE Mode Simulation box must be checked during generation of design example.
    sh xcelium_setup.sh USER_DEFINED_VERILOG_COMPILE_OPTIONS="+define+gdrb_GDR_PCIE_SS_DV\ +define+RTLSIM\ +define+IP7581SERDES_UX_SIMSPEED\ +define+SSM_SEQUENCE\ -sv\" USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ps" USER_DEFINED_SIM_OPTIONS="-input\ @run" | tee simulation.log
    For FASTSIM mode:
    sh xcelium_setup.sh USER_DEFINED_VERILOG_COMPILE_OPTIONS="+define+RTLSIM\ +define+IP7581SERDES_UX_SIMSPEED\ +define+SSM_SEQUENCE\ -sv\" USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ps" USER_DEFINED_SIM_OPTIONS="-input\ @run" | tee simulation.log
    For non-FASTSIM mode:
    sh xcelium_setup.sh USER_DEFINED_VERILOG_COMPILE_OPTIONS="+define+RTLSIM\ +define+SSM_SEQUENCE\ -sv\" USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ps" USER_DEFINED_SIM_OPTIONS="-input\ @run" | tee simulation.log
    Note: The commands above are single-line commands.
  2. A successful simulation ends with the following message in the simulation.log file that was generated.
    "Simulation stopped due to successful completion!"