F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Performance and Resource Utilization 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Analog Parameter Settings 2.5. Reference and System PLL Clock for your IP Design 2.6. Simulating the IP Core 2.7. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Reference and System PLL Clock for your IP Design x
2.5.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control 4.8. 32-bit Soft CWBIN Counters
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

5.1. Clock and Reset Interface Signals

Table 22.  Clock and Reset Interface Signals
Signal Name Width (Bits) I/O Direction Available In Description
pll_ref_clk 1 Input Interlaken and Interlaken Look-aside mode F-tile reference clock source.

Connect to out_refclk_fgt_<n> output of F-Tile Reference and System PLL Clocks Intel FPGA IP core. For more information, refer to System PLL Configuration.

tx_usr_clk 1 Input Interlaken mode Transmit side user data interface clock. The lower frequency of tx_usr_clk increases the latency of data path. You can also connect it to clk_tx_common.
rx_usr_clk 1 Input Interlaken mode Receive side user data interface clock. The lower frequency of rx_usr_clk increases the latency of data path. You can also connect it to clk_rx_common.
clk_tx_common 1 Output Interlaken and Interlaken Look-aside mode Transmit PCS common lane clock driven by the SERDES transmit PLL.
clk_rx_common 1 Output Interlaken and Interlaken Look-aside mode Receive PCS common lane clock driven by CDR in transceiver.

The valid frequencies for clk_rx_common are same as clk_tx_common.

sysclk 1 Input Interlaken and Interlaken Look-aside mode This clock signal is only available in PAM4 IP core variations. Connect to out_systempll_clk_<m> output of F-Tile Reference and System PLL Clocks Intel FPGA IP core. For more information, refer to System PLL Configuration.
mac_clkin 1 Input Interlaken and Interlaken Look-aside mode This clock signal is only available in PAM4 IP core variations. This signal must be driven by a PLL and must use the same clock source that drives the pll_ref_clk.

The frequency for mac_clkin is 395.833 MHz.

mac_pll_locked 1 Input Interlaken and Interlaken Look-aside mode Lock indicator for the PLL that generates mac_clkin.
reset_n 1 Input Interlaken and Interlaken Look-aside mode Active-low asynchronous reset signal for IP only. You must put the IP in reset when resetting the F-tile to prevent IP corruption while waiting for F-tile to be fully in reset.
tx_rst_n 1 Input Interlaken and Interlaken Look-aside mode Active low asynchronous reset for F-tile. This reset drives the tx_desired_state of SRC.
rx_rst_n 1 Input Interlaken and Interlaken Look-aside mode Active low asynchronous reset for F-tile. This reset drives the rx_desired_state of SRC. When you perform a Serial Internal Loopback FGT Attribute Command5, this reset must be held low until TX is fully out-of-reset.
tx_rst_ack_n 1 Output Interlaken and Interlaken Look-aside mode Active low asynchronous reset acknowledge signal. Indicates that soft reset controller has successfully entered reset mode for TX side and you can now release the tx_rst_n signal. This signal stays low until you release the tx_rst_n signal.
rx_rst_ack_n 1 Output Interlaken and Interlaken Look-aside mode Active low asynchronous reset acknowledge signal. Indicates that soft reset controller has successfully entered reset mode for RX side and you can now release the rx_rst_n signal. This signal stays low until you release the rx_rst_n signal.
tx_usr_srst 1 Output Interlaken and Interlaken Look-aside mode Transmit-side reset output signal. Indicates the transmit side user data interface is under reset. This signal is synchronous with tx_usr_clk.
rx_usr_srst 1 Output Interlaken and Interlaken Look-aside mode Receive-side reset output signal. Indicates the receive side user data interface is under reset. This signal is synchronous with rx_usr_clk.
5 For more details, refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide 3.14.2.2. FGT Attribute Access Method.
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