F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

ID 816968
Date 4/01/2024
Public

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 5.0.0
The F-Tile Low Latency 50G Ethernet Intel® FPGA IP provides a design example which allows you to:
  • Compile the design — to get an estimate IP core area and timing
  • Simulate the design — to verify the IP core functionality through simulation
  • Test the design on hardware — to test the design on the Agilex™ 7 I-Series Transceiver-SoC Development Kit
When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Steps for the Design Example