Intel® Agilex™ Variable Precision DSP Blocks User Guide

ID 683037
Date 11/17/2022
Public

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5.5.3. Pre-adder Tab

Table 48.  Pre-adder TabThese parameters are only available in m18×18_full, m18×18_sumof2, m18×18_systolic, and, m27×27 operational modes.
Parameter IP Generated Parameter Value Default Value Description
'ay' operand source operand_source_may

Input

Preadder

Input

Select the operand source for ay input bus.

To enable pre-adder block, select Preadder.

'by' operand source operand_source_mby

Input

Preadder

Input

Select the operand source for by input bus.

To enable pre-adder block, select Preadder.

Set top pre-adder operation to subtraction preadder_subtract_a

No

Yes

No

Specify the operation for top pre-adder.

Select Yes to use top pre-adder as a subtractor.

Select No to use top pre-adder as an adder.

Set bottom pre-adder operation to subtraction preadder_subtract_b

No

Yes

No

Specify the operation for bottom pre-adder.

Select Yes to use bottom pre-adder as a subtractor.

Select No to use bottom pre-adder as an adder.

Data 'z' Configuration
'az' input bus width az_width 0–26 0

Specify the width of az input bus.

Enable 'az' input register az_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for az input register.

'bz' input bus width bz_width 0–18 0

Specify the width of bz input bus.

Enable 'bz' input register bz_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for bz input register.