JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

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ID 683094
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with NIOS Control Unit 1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with NIOS Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Platform Designer (Standard) System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Platform Designer (Standard) System Component x
1.7.1.1.1. JESD204B Subsystem in Platform Designer (Standard) 1.7.1.1.2. Nios II Subsystem in Platform Designer (Standard) 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Platform Designer (Standard) Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B Intel® FPGA IP Design Example User Guide

1.7.9.3.1. Editing the Platform Designer (Standard) Project

  1. Open the top level system, jesd204b_ed_qsys.qsys, in Platform Designer (Standard).
  2. Each JESD204B link is represented by a single jesd204b_subsystem instantiation. To implement multi-links in Platform Designer (Standard), duplicate the jesd204b_subsystem instantiations. Right-click the jesd204b_subsystem_0 module and select Duplicate. This duplicates the jesd204b_subsystem_0 module to a new module called jesd204b_subsystem_1.
  3. Connect the jesd204b_subsystem_1 ports as shown in the table below. Any ports not described in the table below should be exported. To export a port, click the Double-click to export label in the Export column of the System Contents tab.
    Ports for jesd204b_subsystem_1 Module Connection
    device_clk device_clk.clk
    do_not_connect_reset_0 mgmt_clk.clk_reset
    do_not_connect_reset_1 mgmt_clk.clk_reset
    do_not_connect_reset_2 mgmt_clk.clk_reset
    frame_clk frame_clk.clk
    jesd204b_jesd204_rx_int nios_subsystem.nios2_d_irq
    jesd204b_jesd204_tx_int nios_subsystem.nios2_d_irq
    link_clk link_clk.clk
    mgmt_clk mgmt_clk.clk
    mgmt_reset reset_controller_0.reset_out
    mm_bridge_s0 nios_subsystem.jesd204b_subsystem_mm_bridge_0_m0
    reset_seq_irq nios_subsystem.nios2_d_irq
    reset_seq_pll_reset (Do not connect)
    reset_seq_reset_in0 reset_controller_0.reset_out
  4. Adjust the interrupt priorities of the interrupt ports (jesd204b_jesd204_rx_int, jesd204b_jesd204_tx_int, and reset_seq_irq) in the new jesd204b_subsystem_1 module to meet your system specifications. Click and edit the priority number of the relevant ports in the IRQ column of the System Contents tab. The lower the priority number, the higher the priority.
  5. Assign the address map of the jesd204b_subsystem_1 module in the Address Map tab. Bits 16-19 of the nios_subsystem-to-jesd204b_subsystem Avalon-MM bridge are reserved to support multi-links. Assign the address map according to the figure shown below. Bits 16-19 in the address map denotes the link indicator. For subsequent links, increment the link indicator accordingly. The system can support up to 16 links.
    Figure 31. Multi-Link Address Map
  6. Repeat steps 2 – 5 for subsequent links in your design.
  7. Click Generate HDL to generate the design files needed for Quartus compilation.
  8. After the HDL generation is completed, click Finish to save your Platform Designer (Standard) settings and exit the Platform Designer (Standard) window.
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