Intel® Quartus® Prime Pro Edition User Guide: Third-party Synthesis

ID 683122
Date 3/28/2022
Public

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1.8.1. Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files

The IP Catalog generates a Verilog HDL instantiation template file <output file>_inst.v and a hollow-body black box module declaration <output file>_bb.v for use in your Precision Synthesis design. Incorporate the instantiation template file, <output file>_inst.v, into your top-level design to instantiate the IP core wrapper file, <output file>.v.

Include the hollow-body black box module declaration <output file>_bb.v in your Precision Synthesis project to describe the port connections of the black box. Adding the IP core wrapper file <output file>.v in your Precision Synthesis project is optional, but you must add it to your Intel® Quartus® Prime project along with the Precision Synthesis generated EDIF or VQM netlist.

Alternatively, you can include the IP core wrapper file <output file>.v in your Precision Synthesis project and turn on the Exclude file from Compile Phase option in the Precision Synthesis software to exclude the file from compilation and to copy the file to the appropriate directory for use by the Intel® Quartus® Prime software during place-and-route.