Intel® Agilex™ SEU Mitigation User Guide

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ID 683128
Date 12/30/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Agilex™ SEU Mitigation Overview 2. Intel® Agilex™ CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel® Agilex™ SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel® Agilex™ SEU Mitigation User Guide Archives 7. Document Revision History for the Intel® Agilex™ SEU Mitigation User Guide
1. Intel® Agilex™ SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Intel® Agilex™ CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Intel® Agilex™ SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Enabling Priority Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
4.6.6. Injecting Double Adjacent Errors x
4.6.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.6.2. Injecting Double Adjacent Errors: GUI
4.6.7. Injecting SDM ECC Errors x
4.6.7.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.7.2. Injecting SDM ECC Errors: GUI
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection IP Core Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Intel® Agilex™ SEU Mitigation Overview
2. Intel® Agilex™ CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Intel® Agilex™ SEU Mitigation Implementation Guides
5. IP and Software References
6. Intel® Agilex™ SEU Mitigation User Guide Archives
7. Document Revision History for the Intel® Agilex™ SEU Mitigation User Guide

2.3. Scrubbing

Intel® Agilex™ devices support automatic CRAM error correction without reloading the original CRAM contents from an external copy of the original programming bit-stream.

Alternatively, you can scrub through partial reconfiguration by reloading the impacted advanced SEU detection (ASD) region reported by the Advanced SEU Detection Intel® FPGA IP. During the partial reconfiguration process, hold the logic in the partial configuration region in reset until the process completes.

Although scrubbing corrects the SEU error, the SEU error message queue keeps the SEU error message until you retrieve it.

Internal Scrubbing

The internal scrubbing feature automatically corrects single-bit errors.

Intel® recommends that you turn on internal scrubbing. If you do not enable internal scrubbing, the device turns off the SEU mitigation feature for a sector after an error occurs in the sector. Subsequently, the device stops detection of correctable or uncorrectable SEU occurrence in the affected sector.

If you enable the internal scrubbing feature, you must still plan your recovery sequence. Although the scrubbing feature can restore the CRAM array to the intended configuration, a latency period exists between detection and correction of the soft error. During this latency period, the Intel® Agilex™ device may be operating with errors.

For uncorrectable errors, the SDM periodically inserts an error message to the error message queue. The insertion reasserts the SEU_ERROR pin to alert you about the error.

Priority Scrubbing

You can assign portions of the design as high priority sectors for internal scrubbing; the unassigned portions become low priority sectors. The Intel® Agilex™ EDC circuitry detects and corrects errors that occur in the high priority sectors more frequently than the other sectors.

The EDC operation for the priority sectors and non-priority sectors run in parallel when priority scrubbing is enabled. The sectors in group 0 of both the priority sectors and non-priority sectors run the EDC process at time T0. This is followed by the EDC operation of sectors in group 1 of both the priority sectors and non-priority sectors at time T1, sectors in group 2 at time T2, followed by the sectors of the remaining group until the last available group. This corresponds to 1 complete cycle of the EDC process.

For an Intel® Agilex™ device with a total of 30 sectors and the maximum number of sectors allowed to run EDC concurrently, Smax = 5, Intel® Quartus® Prime will determine the number of groups for the priority sectors, GP and non-priority sectors, GN based on the number of priority sectors, P and non-priority sectors, N. Within GP, there is at most Smax-1 number of sectors allocated so that there is at least one sector slot left for the normal sector to run concurrently.

If P≤Smax-1, then GP = 1 and GN is determined by allocating N to the vacant sector slots. For example, P+N = 30, where P = 2 and N = 28, as shown on the left side of the following figure. Since P≤Smax-1, then GP = 1. Two sector slots are occupied by the priority sectors and three sector slots are occupied by the non-priority sectors. GN = 10, is determined by allocating N into three sector slots. The priority sectors only need one unit of time to complete the EDC process compared to the non-priority sectors which need 10 units of time.

If P>Smax-1, then GP and GN are determined by allocating P equally into Smax-1 and N to the last vacant sector slot. For example, P = 6 and N = 24 as shown on the right side of the following figure. Since P>Smax-1, then GP = 2 where the priority sectors are divided equally. Three sector slots are occupied by the priority sectors and two sector slots are occupied by the non-priority sectors, resulting in GN = 12. The priority sectors only need two units of time to complete the EDC process compared to the non-priority sectors which need 12 units of time.

With priority scrubbing, priority sectors will undergo more frequent SEU detection and correction compared to non-priority scrubbing. This provides faster SEU detection and correction for critical design modules. The interval time for priority sectors is always the minimum interval that the Intel® Agilex™ device is capable of, regardless of the user setting of the Minimum SEU Interval in Device and Pin Options. For example, the interval time for one priority sector is always 2160 microseconds regardless if the Minimum SEU Interval is set to 0 or 10000 microseconds.

A warning message is prompted in Intel® Quartus® Prime when P exceeds a certain threshold which causes the priority sectors to require a longer time to complete one cycle of EDC process compared to the non-priority sectors.

Figure 2. Priority Scrubbing
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