Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.6. Viewing Routing and Timing Delays

Right-click any node and click Locate > Locate in Chip Planner to visualize and adjust I/O timing delays and routing between user I/O pads and VCC, GND, and VREF pads. The Chip Planner graphically displays logic placement, Logic Lock regions, relative resource usage, detailed routing information, fan-in and fan-out, register paths, and high-speed transceiver channels. You can view physical timing estimates, routing congestion, and clock regions. Use the Chip Planner to change connections between resources and make post-compilation changes to logic cell and I/O atom placement. When you select items in the Pin Planner, the corresponding item is highlighted in Chip Planner.