AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design

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ID 683167
Date 5/19/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Functional Description 1.4. Hardware Testing 1.5. TCL Script 1.6. Interface Signals 1.7. Configuration Registers and Status Registers 1.8. Regenerating Triple-Speed Ethernet Intel® FPGA IP 1.9. Document Revision History for AN 830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
1.3. Functional Description x
1.3.1. Design Components 1.3.2. Clocking Scheme 1.3.3. Reset Scheme
1.4. Hardware Testing x
1.4.1. Test Case—Internal MAC Loopback 1.4.2. Test Case— Avalon® Streaming Reverse Loopback
1.5. TCL Script x
1.5.1. Configuration Script 1.5.2. Ethernet Packet Generator Script
1. Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices

1.3.1. Design Components

Table 1.  Design Components
Component Description
Triple-Speed Ethernet Intel® FPGA IP
  • This IP provides an integrated Ethernet MAC, PCS, and PMA solution for Ethernet applications.
  • During data transmission, the Triple-Speed Ethernet Intel® FPGA IP transmits Ethernet packets from Avalon® streaming interface to a 1.25-Gbps serial LVDS I/O interface and the Ethernet packets receiving operation is done with the opposite way.
Ethernet Packet Generator
  • This module is a Platform Designer custom component that generates Ethernet packets.
  • It consists of sub-components such as Ethernet packet generation block, CRC generator, Avalon® memory-mapped registers, and shift register.
Ethernet Packet Monitor
  • This module is a Platform Designer custom component that verifies the payload of all received packets and collects the statistics of each received packet such as number of bytes received.
  • It consists of sub-components such as CRC checker and Avalon® memory-mapped registers.
Error Adapter
  • This adapter is a Platform Designer custom component that used to connect mismatched Avalon® streaming source and sink interface.
  • By using this adapter, data source and data sink with different bit width can be connected together. For RX-to-TX Avalon® streaming reverse loopback in this reference design, ff_tx_err is a 1-bit error signal while rx_err is a 6-bit error signal.
  • This adapter can match the error conditions that are handled by the Avalon® streaming source and Avalon® streaming sink.
Avalon® Streaming Multiplexer
  • This multiplexer is a Platform Designer custom component that accepts data on its two Avalon® streaming sink interfaces and multiplexes the data for transmission on its Avalon® streaming source interface.
  • One of the Avalon® streaming sink interface is connected to the Avalon® streaming source interface of Ethernet Packet Generator (For forward MAC loopback) and another Avalon® streaming sink interface is connected to the Avalon® streaming source interface of Error Adapter (for reverse loopback).
  • The packets on Avalon® streaming source interface of this multiplexer will be transmitted to Triple-Speed Ethernet Intel® FPGA IP.
Avalon® Streaming Splitter
  • This splitter is a Platform Designer custom component that accepts data from Triple-Speed Ethernet Intel® FPGA IP through Avalon® streaming sink interface and splits the data on its two Avalon® streaming source interfaces.
  • One of its Avalon® Streaming source interface is connected to the Avalon® streaming sink interface of Ethernet Packet Monitor (for forward MAC loopback) and another Avalon® streaming source interface is connected to the Avalon® streaming sink interface of Error Adapter (for reverse loopback).
JTAG to Avalon® Master Bridge Intel® FPGA IP This IP provides a connection between System Console and Platform Designer system through the physical interface. The System Console initiates Avalon® memory-mapped transactions by sending encoded streams of bytes through bridge’s physical interface.
IOPLL Intel® FPGA IP
  • This IP generates a 100 MHz PLL output clock (clk_100M).
  • This output clock is the clock source for Platform Designer system. All components in this reference design use this output clock.
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