25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683252
Date 6/18/2020
Public
Document Table of Contents
Document Table of Contents x
1. 25G Ethernet Intel® FPGA IP Quick Start Guide 2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices 3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices 4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices 5. 25G Ethernet Intel® FPGA IP Design Example References 6. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 7. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. 25G Ethernet Intel® FPGA IP Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench x
1.3.1. Procedure
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure
1.5. Changing Target Device in Hardware Design Example x
1.5.1. Procedure
1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware x
1.6.1. Procedure
2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature 2.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
2.6. Hardware Testing x
2.6.1. Test Procedure—Design Example Without the IEEE 1588v2 Feature 2.6.2. Test Procedure—Design Example with the IEEE 1588v2 Feature
3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Compilation 3.6. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature 3.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
3.6. Hardware Testing x
3.6.1. Test Procedure—Design Example With and Without the IEEE 1588v2 Feature
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Compilation 4.6. Hardware Testing
4.3. Functional Description x
4.3.1. Design Components
4.4. Simulation x
4.4.1. Testbench 4.4.2. Simulation Design Example Components 4.4.3. Test Case
4.6. Hardware Testing x
4.6.1. Test Procedure
5. 25G Ethernet Intel® FPGA IP Design Example References x
5.1. Design Example Interface Signals 5.2. Design Example Registers 5.3. Using Transceiver Toolkit on H-Tile Production Device
1. 25G Ethernet Intel® FPGA IP Quick Start Guide
2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices
3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices
5. 25G Ethernet Intel® FPGA IP Design Example References
6. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

2.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature

The simulation test case performs the following actions:

  1. Instantiates 25G Ethernet Intel® FPGA IP and ATX PLL.
  2. Starts up the design example with an operating speed of 25G.
  3. Waits for RX clock and PHY status signal to settle.
  4. Prints PHY status.
  5. Sends and receives 10 valid data on 25G speed.
  6. Performs channel reset and switches to 10G speed.
  7. Waits for RX clock and PHY status signal to settle.
  8. Prints PHY status.
  9. Sends and receives another 10 valid data on 10G speed.
  10. Performs channel reset and switches to 25G speed.
  11. Waits for RX clock and PHY status signal to settle.
  12. Prints PHY status.
  13. Sends and receives another 10 valid data on 25G speed.
  14. Analyzes the results. The successful testbench displays "Simulation PASSED.".

The following sample output illustrates a successful simulation test run: 

Waiting for RX alignment
RX deskew locked
RX lane alignmnet locked
TX enabled
** Sending Packet            1...
** Sending Packet            2...
** Sending Packet            3...
** Sending Packet            4...
** Sending Packet            5...
** Sending Packet            6...
** Sending Packet            7...
** Sending Packet            8...
** Received Packet           1...
** Received Packet           2...
** Sending Packet            9...
** Sending Packet           10...
** Received Packet           3...
** Received Packet           4...
** Received Packet           5...
** Received Packet           7...
** Received Packet           8...
** Received Packet           9...
** Received Packet          10...
Switching to 10G mode: 10G Reconfig start
Switching to 10G mode: 10G Reconfig End
Waiting for RX alignment
RX deskew locked
RX lane alignment locked
TX enabled
** Sending Packet            1...
** Sending Packet            2...
** Sending Packet            3...
** Sending Packet            4...
** Sending Packet            5...
** Sending Packet            6...
** Sending Packet            7...
** Sending Packet            8...
** Received Packet           1...
** Received Packet           2...
** Sending Packet            9...
** Sending Packet           10...
** Received Packet           3...
** Received Packet           4...
** Received Packet           5...
** Received Packet           7...
** Received Packet           8...
** Received Packet           9...
** Received Packet          10...
Switching to 25G mode: 25G Reconfig start
Switching to 25G mode: 25G Reconfig End
Waiting for RX alignment
RX deskew locked
RX lane alignment locked
TX enabled
** Sending Packet            1...
** Sending Packet            2...
** Sending Packet            3...
** Sending Packet            4...
** Sending Packet            5...
** Sending Packet            6...
** Sending Packet            7...
** Sending Packet            8...
** Received Packet           1...
** Received Packet           2...
** Sending Packet            9...
** Sending Packet           10...
** Received Packet           3...
** Received Packet           4...
** Received Packet           5...
** Received Packet           7...
** Received Packet           8...
** Received Packet           9...
** Received Packet          10...
**
** Testbench complete.
**
Level Two Title