AN 806: Hierarchical Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

Download PDF
ID 683278
Date 2/04/2021
Public
Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Partial Reconfiguration Controller IP Step 6: Defining Personas Step 7: Creating Revisions Step 8: Compiling the Base Revision Step 9: Preparing the PR Implementation Revisions for Parent PR Partition Step 10: Preparing the PR Implementation Revisions for Child PR Partitions Step 11: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 7: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 11: Programming the Board x
Programming the Child PR Region Troubleshooting PR Programming Errors
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board

Document Revision History for Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board

Document Version Intel® Quartus® Prime Version Changes
2021.02.04 20.3
  • Updated version support to 20.3.
  • Updated design partitions screenshot in Creating Design Partitions topic.
  • Updated step 2 in Allocating Placement and Routing Regions for PR Partitions topic.
  • Updated step 1 and step 4 in Adding the Partial Reconfiguration Controller IP topic.
  • Updated step 2 code sample in Updating the Top-Level Design topic.
  • Updated Design Partitions Window screenshot in Step 9: Preparing PR Implementation Revisions topic.
2019.07.15 19.1
  • Updated version support to 19.1.
  • Updated default .qdb export location from output_files to project directory.
  • Updated for changes to Design Partition command submenu changes, including change of "periphery reuse core" to "reserved core."
  • Updated references to the official name of Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP.
  • Updated QSF examples for latest version.
  • Updated all screenshots for latest version.
  • Updated references to Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration.
2018.09.24 18.1
  • Updated sections - Step 3: Creating Design Partitions, Step 8: Compiling the Base Revision and Exporting the Static Region, Step 9: Preparing the PR Implementation Revisions for Parent PR Partition, and Step 10: Preparing the PR Implementation Revisions for Child PR Partitions with the new PR flow that eliminates the need for manual export of finalized snapshot of the static region.
  • Other minor text edits and image updates.

2018.05.07

18.0
  • Compilation flow change
  • Other minor text edits

2017.11.06

17.1
  • Updated the Reference Design Requirements section with software version
  • Updated the Flat Reference Design without PR Partitioning figure with design block changes
  • Updated the Reference Design Files table with information on the Top_counter.sv module
  • Updated the Partial Reconfiguration IP Core Integration figure with design block changes
  • Updated the figures - Design Partitions Window and Logic Lock Regions Window to reflect the new GUI
  • File name changes
  • Text edits

2017.05.08

17.0

Initial release of the document
Level Two Title