HDMI Intel® Cyclone® 10 GX FGPA IP Design Example User Guide

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ID 683309
Date 1/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices 2. HDMI Design Example 3. HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI Design Example x
2.1. HDMI RX-TX Retransmit Design Block Diagram 2.2. Design Components 2.3. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.4. Clocking Scheme 2.5. Interface Signals 2.6. Design RTL Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices
2. HDMI Design Example
3. HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2024.01.26 21.1 19.6.0
  • Added a step in the Compiling and Testing the Design topic to configure the OUT7 frequency of the Clock Controller.
  • Removed the note regarding support for Bitec HDMI daughter card revisions 4 and 6 from the Hardware and Software Requirementstopic.
2022.09.07 21.1 19.6.0 Edited Disabling HDR Insertion and Filtering chapter to incorporate steps to disable HDR InfoFrame insertion and filtering for TMDS mode design.
2021.09.15 21.1 19.6.0 Removed references to ncsim
2021.04.01 21.1 19.6.0

Updated Figure HDMI RX-TX Block Diagram to add a connection from Transceiver Arbiter to TX top

2020.09.28 20.3 19.5.0
  • Updated the directory structure for Intel® Cyclone® 10 GX design example and the generated files list in the Directory Structure section.
  • Updated the version in the Hardware and Software Requirements section.
  • Updated the simulation message in the Simulating the Design section.
  • Updated the design file name and board information in the Compiling and Testing the Design section.
  • Updated the feature description to include that the design allows run-time control through DIP switch and push-button to manage the HDMI TX core signals in the HDMI Design Example section.
  • Updated the block diagrams for the HDMI design example in the HDMI Design Example and Clocking Scheme sections.
  • Updated the description for the RX and TX core components and removed the description for the PIO component from the Design Components section.
  • Updated the clock and reset signal names in the Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering section.
  • Updated the description for the RX CDR reference clock signals in the Clocking Scheme section.
  • Removed irrelevant signals, and added or edited the description of the following HDMI 2.0 design example signals in the Interface Signals section:
    • usb_refclk_p
    • fmcb_la_tx_p_11
    • fmcb_la_rx_n_9
    • reset_xcvr_powerup
    • fr_clk
    • nios_tx_i2c* signals
    • hdmi_ti_i2c* signals
    • tx_i2c_avalon* signals
    • clock_bridge_0_in_clk_clk
    • reset_bridge_0_reset_reset_n
    • i2c_master* signals
    • nios_tx_i2c* signals
    • i2c_master_i2c_serial* signals
    • powerup_cal_done_export
    • rx_pma_cal_busy_export
    • rx_pma_ch_export
    • rx_pma_rcfg_mgmt* signals
    • rx_pma_wairequest_export
    • rx_rcfg_en_export
    • rx_rst_xcvr_export
  • Added the following parameters in the Design RTL Parameters section:
    • EDID_RAM_ADDR_WIDTH
    • POLARITY_INVERSION
  • Added a note that the simulation testbench is not supported for designs with the Include I2C parameter enabled and updated the simulation message in the Simulation Testbench section.
  • Updated the Upgrading Your Design section.
2018.10.25 18.1 18.1
  • Added generated files for the tx_control_src folder: ti_i2c.c and ti_i2c.h
  • Added a new design RTL parameter, BITEC_DAUGHTER_CARD_REV, to enable you select the revision of the Bitec HDMI daughter card.
  • Added limitation that the HDMI RX core does not perform word alignment for HDMI 2.0 resolutions (data rate > 3.4 Gbps). Use Transceiver PCS word aligner and control logic to achieve fast word alignment.
  • Added the following new signals for Bitec daughter card revision 11.
    • hdmi_tx_ti_i2c_sda
    • hdmi_tx_ti_i2c_scl
    • oc_i2c_master_ti_avalon_anti_slave_address
    • oc_i2c_master_ti_avalon_anti_slave_write
    • oc_i2c_master_ti_avalon_anti_slave_readdata
    • oc_i2c_master_ti_avalon_anti_slave_writedata
    • oc_i2c_master_ti_avalon_anti_slave_waitrequest
    • oc_i2c_master_ti_avalon_anti_slave_chipselect
  • Added a section about Upgrading Your Design.
  • Edited the errors in the description for user_dipsw[0] and user_pb[1] in the Hardware Setup section.
2017.12.25 17.1.1 17.1.1 Initial release.
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