AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

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ID 683343
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY x
Features Requirements Design Example Walkthrough Components Parameters Design Example Testbench Clocking Scheme Reset Scheme Interface Signals Register Map Document Revision History for Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Design Example Walkthrough x
Setting Up the Design Examples Changing Number of Channels Configuring PHY Speed IP Regeneration
Configuring PHY Speed x
Changing Speed between 10G and 1G in 1000BaseX mode Changing Speed between 1G, 100M, and 10M SGMII
Design Example Testbench x
Testbench Components Testbench Files Simulating Testbench Test Case
Simulating Testbench x
Using ModelSim Simulator Using VCS Simulator
Test Case x
Test Scenario for Design Example without IEEE 1588v2 Test Scenario for Design Example with IEEE 1588v2
Clocking Scheme x
Clocking Diagram Sync-E Support
Sync-E Support x
Enable Ref Clock Sharing Disable Ref Clock Sharing
Reset Scheme x
Design Example without IEEE 1588v2 Design Example with IEEE 1588v2
Design Example without IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Design Example with IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals MDIO Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals ToD Interface Signals
Register Map x
Master TOD 1G TOD 10G TOD PHY 1G/10G MAC
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

Clock and Reset Interface Signals

The following table lists the clock and reset interface signals. These interface signals are applicable to both design examples.

Table 6.   Clock and Reset Interface Signals
Signal Direction Width Description
mm_clk input 1 Configuration clock for Avalon-MM interface. Frequency is 125 MHz.
pll_ref_clk_1g[] input [NUM_UNSHARED_CHANNELS] Reference clock for the TX PLL in 1G mode. Frequency is 125 MHz.
pll_ref_clk_10g[] input [NUM_UNSHARED_CHANNELS] Reference clock for the TX PLL in 10G mode. Frequency is 644.53125 MHz.
cdr_ref_clk_1g[] input [NUM_UNSHARED_CHANNELS] Reference clock for the RX PLL in 1G mode. Frequency is 125 MHz.
cdr_ref_clk_10g[] input [NUM_UNSHARED_CHANNELS] Reference clock for the RX PLL in 10G mode. Frequency is 644.53125 MHz.
channel_reset_n input [NUM_CHANNELS] To reset individual Ethernet channel. This does not impact the components running at multi_channel level, e.g. master TOD, master PPS and fPLLs. Asynchronous and active low signal.
master_reset_n input 1 To reset the whole design example. Asynchronous and active low signal.
xgmii_clk output [NUM_UNSHARED_CHANNELS] Clock used for single data rate (SDR) XGMII TX & RX interface in between MAC and PHY. This clock is also used for Avalon-ST interface. Frequency is 156.25MHz.
rx_recovered_clk output [NUM_CHANNELS] This is the RX clock, which is recovered from the received data.
Level Two Title