AN 647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design

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ID 683344
Date 12/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design 2. Document Revision History
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design x
1.1. System Architecture 1.2. Interface Signals 1.3. Base Addresses and Configuration Registers 1.4. Running the Reference Designs
1.1. System Architecture x
1.1.1. Design Components
1.1.1. Design Components x
1.1.1.1. Ethernet Packet Generator 1.1.1.2. Ethernet Packet Monitor
1.3. Base Addresses and Configuration Registers x
1.3.1. Ethernet Packet Generator Configuration Registers 1.3.2. Ethernet Packet Monitor Configuration Registers
1.4. Running the Reference Designs x
1.4.1. Hardware and Software Requirements 1.4.2. Internal MAC Loopback Test 1.4.3. Avalon-ST Reverse Loopback Test 1.4.4. Tcl Script
1.4.4. Tcl Script x
1.4.4.1. Configuration Script 1.4.4.2. Ethernet Packet Generator Script
1.4.4.2. Ethernet Packet Generator Script x
1.4.4.2.1. JTAG Connection Port for Altera Devices
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design
2. Document Revision History

1.1. System Architecture

The reference designs demonstrate fully operational subsystems that integrate the Triple-Speed Ethernet IP core for Ethernet applications.

Figure 1. Reference Design with SGMII Interface—Arria 10 DevicesThe figure shows a high-level block diagram of the reference design implementing the SGMII interface with Arria 10 devices.

Figure 2. Reference Design with SGMII Interface—Stratix V GX DevicesThe figure shows a high-level block diagram of the reference design implementing the SGMII interface with Stratix V GX devices.

Figure 3. Reference Design with RGMII Interface—Arria V GX and Cyclone V GX DevicesThe figure shows a high-level block diagram of the reference design implementing the RGMII interface with Arria V GX and Cyclone V GX devices.

Section Content
Design Components

Level Two Title