AN 919: Improving Quality of Results with Design Assistant

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ID 683369
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
Improving Quality of Results with Design Assistant Document Revision History for AN 919: Improving Quality of Results with Design Assistant Appendix A: Running Design Assistant Appendix B: Design Assistant Rules
Improving Quality of Results with Design Assistant x
About Design Assistant About the Design Assistant Design Example Fixing SDC and CDC Rules in the Design Assistant Design Example Fixing Other Faults in the Design Assistant Design Example
Appendix A: Running Design Assistant x
Running Design Assistant
Appendix B: Design Assistant Rules x
Timing Closure Rules Clock Domain Crossing and Reset Domain Crossing Rules Intrinsic Margin Rules Combinatorial Logic Levels Reducing High Fan-out Nets Hyper-Retimer Restrictions Initial Power-Up Conditions Rules Reset Release Intel FPGA IP
Reducing High Fan-out Nets x
Duplication Rules Tension and Span Rules
Initial Power-Up Conditions Rules x
Removing Initial Power-Up Conditions
Improving Quality of Results with Design Assistant
Document Revision History for AN 919: Improving Quality of Results with Design Assistant
Appendix A: Running Design Assistant
Appendix B: Design Assistant Rules

Duplication Rules

The following rules detect an issue with hierarchical tree duplication:

  • TMC-20500 – Hierarchical Tree Duplication was Shallower Than Possible
  • TMC-20501 – Hierarchical Tree Duplication was Shallower than Requested

Refer to the Intel Quartus Prime Help for more information about these rules.

If you are familiar with the design, you can make duplication decisions. Duplicate the register directly in the RTL, using dont_merge or preserve_syn_only to prevent synthesis from optimizing them away. For example, duplicating high fan-out broadcast signals by module.

The following are high fan-out rules:

  • HRR-10115 – Nets with fan out exceeding threshold
  • HRR-10003 – Registers with high fan-out non-globals
  • TMC-20051 – High fan-out net drives RAM control signals.

To reduce fan-out on a RAM control signal, divide the memory into smaller chunks and send each duplicated control signal to its own memory. This technique works on wide memories.

Figure 20. A 256x2048 Memory with Large Fan-out on a Write Enable
Figure 21. Duplicated Write Enable and Split Memory to Reduce Fan-out
Table 3.  Duplication Rejection RulesThe following rules report if the tool rejects duplication or if the design requires further duplication. The tool can reject duplication, for a placement constraint or for other connectivity reasons. You can identify issues with duplication in the planned netlist.
Rule Description
TMC-20550 – Duplicate Candidate Rejected for Placement Constraint Registers with a tight placement constraint such as logic lock region, clock region, or location assignments cannot be automatically duplicated. Relax the constraint to include the register’s fan-outs or use the duplication techniques.
TMC-20551 – Automatically Discovered Duplication Candidates Likely Requires More Duplication Quartus® Prime duplicates candidate registers automatically. If fan out is still large, apply further duplication techniques to reduce fan-out further.

Rule TMC-20552 detects rejected duplication candidates. Rejection reasons include:

  • Registers drive global signals or clock signals.
  • Registers have timing assignments or exceptions applied to them.
  • Registers have a preserve attribute or a PRESERVE_REGISTER assignment.
  • Registers are marked as don't touch.
  • Registers drive or are driven by other partitions.
Figure 22. Duplication SummaryThe fitter place stage produces a duplication summary, which shows duplication candidates and their duplication status.
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