• The Speed grade for the device. The displayed speed grade should match the selected device in Intel® Quartus® Prime Project for User.
• The desired HBM location.
• The desired number of HBM channels. This determines the number of Traffic Generator pairs. One AXI switch component/module is attached to two neighboring HBM channels. For each HBM channel pair (for example, CH0 and CH1), there is a parameter to enable one AXI switch for channel 0 and 1. If both HBM channel 0 and channel 1 are enabled, you can choose to enable the AXI switch for this channel pair and leave the rest as direct AXI connection to AXI master (user logic side).
• The desired HBM2 memory clock frequency.
• The PLL reference clock frequency. This reference clock is for the High Bandwidth Memory (HBM2) Interface Intel FPGA IP subsystem and should match the PLL reference clock frequency that you provide to the hbm_0_example_design_pll_ref_clk_clk pin.
• The Reference clock frequency for example design core clock PLL. This reference clock is for the core clock PLL instantiated in the design example file as an example external clock that feeds the ext_core_clock port of the High Bandwidth Memory (HBM2) Interface Intel FPGA IP. The value should match the PLL reference clock frequency that you supply to the core_clk_iopll_ref_clk_clk pin.
• The desired Core clock frequency. The value determines the output clock of the core clock PLL instantiated in the design example file as an example external clock that feeds the ext_core_clock port of the High Bandwidth Memory (HBM2) Interface Intel FPGA IP. The clock eventually clocks the Traffic Generator and any other components clocked by the wmc_clk_0_clk clock of the High Bandwidth Memory (HBM2) Interface Intel FPGA IP

For initial project investigations, you may use the default settings on the Diagnostic tab.

For hardware testing using the synthesizable design example, check the Enable In-System-Sources-and-Probes checkbox to allow you to easily control and monitor the High Bandwidth Memory (HBM2) Interface Intel FPGA IP example design system through the Intel® Quartus® Prime software.

For efficiency testing on both synthesis and simulation designs, check the Use Efficiency Pattern and Enable Efficiency Test Mode checkboxes. Keep both the read count and write count the same to ensure that the validity check passes. Select the Data Sequence (Random/Sequential) option for testing, and check Enable data check for efficiency measurement for data validity check.

For simulation, if you want the simulation to report the efficiency number for each HBM channel that you have enabled, check the Enable Efficiency Monitor checkbox. (For hardware testing using the synthesizable example design project, you should not enable the Efficiency Monitor, as this feature reduces the frequency at which the interface will close timing in the core clock domain.)

You can also use the other parameters on the Diagnostics tab to assist you in evaluating, verifying and debugging the High Bandwidth Memory (HBM2) Interface Intel FPGA IP.

To get the correct design example file sets, ensure that you check either the Simulation or Synthesis checkbox, or both, in the Example Design Files section. The generated design example is a complete HBM2 system consisting of the High Bandwidth Memory (HBM2) Interface Intel FPGA IP and a driver that generates random traffic to validate the memory interface.