JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 5/05/2023
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Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Intel® Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

4.6.1. Transmitter Signals

Figure 24. Transmitter Signal DiagramL denotes the number of lanes.
Table 25.  Transmitter Signals
Signal Width Direction Description
Clocks and Resets
pll_ref_clk

1

Input

Transceiver reference clock signal. The reference clock selection depends on the FPGA device family and data rate.

This signal is only applicable for Arria® V, Cyclone® V, and Stratix® V devices.

txlink_clk

1

Input

TX link clock signal. This clock is equal to the TX data rate divided by 40.

For Subclass 1, you cannot use the output of txphy_clk signal as txlink_clk signal . To sample SYSREF correctly, the core PLL must provide the txlink_clk signal and must be configured as normal operating mode.

txlink_rst_n_reset_n

1

Input

Reset for the TX link clock signal. This reset is an active low signal.

txphy_clk[]

L

Output

TX parallel clock output for the TX transceiver with PCS option in Hard PCS or Soft PCS mode. This clock has the same frequency as txlink_clk signal. For PCS option in PMA Direct mode, this clock is half the frequency of txlink_clk signal.

This clock is output as an optional port for user if the txlink_clk and txframe_clk signals are operating at the same frequency in Subclass 0 operating mode.

tx_digitalreset[] 30

L

Input

Reset for the transceiver PCS block. This reset is an active high signal.

Note: This signal is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
tx_digitalreset_stat[] L Output TX PCS digital reset status port connected to the transceiver reset controller. This signal is applicable only for Intel® Stratix® 10 L-tile and H-tile devices.
tx_analogreset[] 30

L

Input

Reset for the transceiver PMA block. This reset is an active high signal.

Note: This signal is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
tx_analogreset_stat[] L Output TX PMA analog reset status port connected to the transceiver reset controller.
Note: This signal is applicable only for Intel® Stratix® 10 L-tile and H-tile devices.
pll_locked[] 30 L

Output

This is the PLL locked output signal for the hard transceiver of the Arria® V, Cyclone® V, and Stratix® V devices. This signal is asserted to indicate that the TX transceiver PLL is locked.
Input This is the input signal for the Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
Note: This signal is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
tx_cal_busy[] 30

L

Output

TX calibration in progress signal. This signal is asserted to indicate that the TX transceiver calibration is in progress.

Note: This signal is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
pll_powerdown[] 30
  • 1 if bonding mode = "xN"
  • L if bonding mode = feedback_compensation

Input

TX transceiver PLL power down signal.

This signal is only applicable for Arria® V, Cyclone® V, and Stratix® V devices.

tx_bonding_clocks

(Single Channel)

tx_bonding_clocks_ch<0..L-1>[]

(Multiple Channels)

6

Input

The transceiver PLL bonding clocks. The transceiver PLL generation provides these clocks.

This signal is only available if you select Bonded mode for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 L-tile and H-tile devices.

Note: This signal is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
tx_serial_clk0

(Single Channel)

tx_serial_clk0_ch<0..L-1>

(Multiple Channels)

1

Input

The transceiver PLL serial clock. This is the serializer clock in the PMA. The transceiver PLL generation provides these clocks.

This signal is only available if you select Non-bonded mode for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 L-tile and H-tile devices.

Note: This signal is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.

Signal

Width

Direction

Description

Transceiver Interface
tx_serial_data[]

L

Output

Differential high-speed serial output data. The clock is embedded in the serial data stream.

tx_serial_data_n

L

Output

Differential high-speed serial output data. The clock is embedded in the serial data stream. You don't need to connect this signal at the top-level pinout for proper compilation.

Note: This signal is applicable only for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
reconfig_to_xcvr[]
  • (L+1)*70 if bonding mode = "xN"
  • L*140 if bonding mode = feedback compensation

Input

Reconfiguration signals from the Transceiver Reconfiguration Controller IP core to the PHY device.

This signal is only applicable for Arria® V, Cyclone® V, and Stratix® V devices.

You must connect these signals to the Transceiver Reconfiguration Controller IP core regardless of whether run-time reconfiguration is enabled or disabled. The Transceiver Reconfiguration Controller IP core also supports various calibration function during transceiver power up.

reconfig_from_xcvr[]
  • (L+1)*46 if bonding mode = "xN"
  • L*92 if bonding mode = feedback compensation

Output

Reconfiguration signals to the Transceiver Reconfiguration Controller IP core.

This signal is only applicable for Arria® V, Cyclone® V, and Stratix® V devices.

You must connect these signals to the Transceiver Reconfiguration Controller IP core regardless of whether run-time reconfiguration is enabled or disabled. The Transceiver Reconfiguration Controller IP core also supports various calibration function during transceiver power up.

reconfig_clk

reconfig_clk[]

reconfig_clk_ch<0..L-1>

  • 1 if Share Reconfiguration Interface = On
  • L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 1 bit per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Input

The Avalon® memory-mapped clock input. The frequency range is 100–125 MHz.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_reset

reconfig_reset[]

reconfig_reset_ch<0..L-1>

  • 1 if Share Reconfiguration Interface = On
  • L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 1 bit per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Input

Reset signal for the Transceiver Reconfiguration Controller IP core. This signal is active high and level sensitive.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_avmm_address[]

reconfig_avmm_address_ch<0..L-1>[]

Intel® Arria® 10

  • log2L*1024 if Share Reconfiguration Interface = On
  • 10*L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 10 bits per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Intel® Stratix® 10

  • log2L*2048 if Share Reconfiguration Interface = On
  • 11*L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 11 bits per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Input

The Avalon® memory-mapped address.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_avmm_writedata[]

reconfig_avmm_writedata_ch<0..L-1>[]

For all devices except Intel Agilex® 7 and Intel® Stratix® 10 E-tile.

  • 32 if Share Reconfiguration Interface = On
  • 32*L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 32 bits per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

For Intel® Stratix® 10 E-tile devices.

  • 8 if Share Reconfiguration Interface = On
  • 8*L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 8 bits per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Input

The input data.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_avmm_readdata[]

reconfig_avmm_readdata_ch<0..L-1>[]

For all devices except Intel Agilex® 7 and Intel® Stratix® 10 E-tile.

  • 32 if Share Reconfiguration Interface = On
  • 32*L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 32 bits per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.

  • 8 if Share Reconfiguration Interface = On
  • 8*L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 8 bits per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Output

The output data.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_avmm_write

reconfig_avmm_write[]

reconfig_avmm_write_ch<0..L-1>

  • 1 if Share Reconfiguration Interface = On
  • L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 1 bit per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Input

Write signal. This signal is active high.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_avmm_read

reconfig_avmm_read[]

reconfig_avmm_read_ch<0..L-1>

  • 1 if Share Reconfiguration Interface = On
  • L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 1 bit per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Input

Read signal. This signal is active high.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_avmm_waitrequest

reconfig_avmm_waitrequest[]

reconfig_avmm_waitrequest_ch<0..L-1>

  • 1 if Share Reconfiguration Interface = On
  • L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 1 bit per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Output

Wait request signal.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

phy_tx_ready L Output

Signal to indicate the transceiver TX is ready.

Note: This signal is applicable only for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
phy_tx_pma_ready L Output

Signal to indicate the transceiver TX PMA is ready. This signal must be asserted before you assert or deassert any TX resets.

Note: This signal is applicable only for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
phy_tx_rst_n 1 Input

Active-high hard reset signal that resets the transceiver TX interface.

Asserting this signal does not reset the transceiver PMA. Refer to the E-tile Transceiver PHY User Guide about how to reset PMA through the Avalon® memory-mapped reconfiguration interface.

Note: This signal is applicable only for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.

Signal

Width

Direction

Description

Avalon® Streaming Interface
jesd204_tx_link_data[]

L*32

Input

Indicates a 32-bit user data at txlink_clk clock rate, where four octets are packed into a 32-bit data width per lane. The data format is big endian.

The first octet is located at bit[31:24], followed by bit[23:16], bit[15:8], and the last octet is bit[7:0]. Lane 0 data is always located in the lower 32-bit data. If more than one lane is instantiated, lane 1 is located at bit[63:32], with the first octet position at bit[63:56].

jesd204_tx_link_valid

1

Input

Indicates whether the data from the transport layer is valid or invalid. The Avalon® streaming sink interface in the TX core cannot be backpressured and assumes that data is always valid on every cycle when the jesd204_tx_link_ready signal is asserted.

  • 0—data is invalid
  • 1—data is valid
jesd204_tx_link_ready

1

Output

Indicates that the Avalon® streaming sink interface in the TX core is ready to accept data. The Avalon® streaming sink interface asserts this signal on the JESD204B link state of USER_DATA phase. The ready latency is 0.

jesd204_tx_frame_ready

1

Output

Indicates that the Avalon® streaming sink interface in the transport layer is ready to accept data. The Avalon® streaming sink interface asserts this signal on the JESD204B link state of ILAS 4th multiframe and also the USER_DATA phase. The ready latency is 0.

Signal

Width

Direction

Description

Avalon® Memory-Mapped Interface
jesd204_tx_avs_clk

1

Input

The Avalon® memory-mapped interface clock signal. This clock is asynchronous to all the functional clocks in the JESD204B IP core. The JESD204B IP core can handle any cross clock ratio and therefore the clock frequency can range from 75 MHz to 125 MHz.

jesd204_tx_avs_rst_n

1

Input

This reset is associated with the jesd204_tx_avs_clk signal. This reset is an active low signal. You can assert this reset signal asynchronously but must deassert it synchronously to the jesd204_tx_avs_clk signal. After you deassert this signal, the CPU can configure the CSRs.

jesd204_tx_avs_chipselect

1

Input

When this signal is present, the slave port ignores all Avalon® memory-mapped signals unless this signal is asserted. This signal must be used in combination with read or write. If the Avalon® memory-mapped bus does not support chip select, you are recommended to tie this port to 1.

jesd204_tx_avs_address[]

8

Input

For Avalon® memory-mapped slave, the interconnect translates the byte address into a word address in the address space so that each slave access is for a word of data. For example, address = 0 selects the first word of the slave and address = 1 selects the second word of the slave.

jesd204_tx_avs_writedata[]

32

Input

32-bit data for write transfers. The width of this signal and the jesd204_tx_avs_readdata[31:0] signal must be the same if both signals are present

jesd204_tx_avs_read

1

Input

This signal is asserted to indicate a read transfer. This is an active high signal and requires the jesd204_tx_avs_readdata[31:0] signal to be in use.

jesd204_tx_avs_write

1

Input

This signal is asserted to indicate a write transfer. This is an active high signal and requires the jesd204_tx_avs_writedata[31:0] signal to be in use.

jesd204_tx_avs_readdata[]

32

Output

32-bit data driven from the Avalon® memory-mapped slave to master in response to a read transfer.

jesd204_tx_avs_waitrequest

1

Output

This signal is asserted by the Avalon® memory-mapped slave to indicate that it is unable to respond to a read or write request. The JESD204B IP core ties this signal to 0 to return the data in the access cycle.

Signal

Width

Direction

Description

JESD204 Interface
sysref

1

Input

SYSREF signal for JESD204B Subclass 1 implementation.

For Subclass 0 and Subclass 2 mode, tie-off this signal to 0.

sync_n

1

Input

Indicates SYNC_N from the converter device or receiver. This is an active low signal and is asserted 0 to indicate a synchronization request or error reporting from the converter device.

To indicate a synchronization request, the converter device must assert this signal for at least five frames and nine octets.

To indicate an error reporting, the converter device must ensure that the pulse is at least one cycle of the txlink_clk signal or two cycles of the txframe_clk signal (whichever period is longer).

dev_sync_n

1

Output

Indicates a clean synchronization request. This is an active low signal and is asserted 0 to indicate a synchronization request only. The sync_n signal error reporting is being masked out of this signal. This signal is also asserted during software-initiated synchronization.

mdev_sync_n

1

Input

Indicates a multidevice synchronization request. Synchronize signal combination should be done externally and then input to the JESD204B IP core through this signal.

  • For subclass 0—combine the dev_sync_n signal from all multipoint links before connecting to the mdev_sync_n signal.
  • For subclass 1—connect the dev_sync_n signal to the mdev_sync_n signal for each link respectively.

In a single link instance where multidevice synchronization is not needed, tie the dev_sync_n signal to this signal.

somf[] 4 Output

Indicates a start of multiframe.

  • [3]—start of multiframe for jesd204_tx_link_data[31:24]
  • [2]—start of multiframe for jesd204_tx_link_data[23:16]
  • [1]—start of multiframe for jesd204_tx_link_data[15:8]
  • [0]—start of multiframe for jesd204_tx_link_data[7:0]

Signal

Width

Direction

Description

CSR
jesd204_tx_frame_error

1

Input

Optional signal to indicate an empty data stream due to invalid data. This signal is asserted high to indicate an error during data transfer from the transport layer to the TX core.

csr_l[]

5

Output

Indicates the number of active lanes for the link. The transport layer can use this signal as a run-time parameter.

csr_f[]

8

Output

Indicates the number of octets per frame. The transport layer can use this signal as a run-time parameter.

csr_k[]

5

Output

Indicates the number of frames per multiframe. The transport layer can use this signal as a run-time parameter.

csr_m[]

8

Output

Indicates the number of converters for the link. The transport layer can use this signal as a run-time parameter.

csr_cs[]

2

Output

Indicates the number of control bits per sample. The transport layer can use this signal as a run-time parameter.

csr_n[]

5

Output

Indicates the converter resolution. The transport layer can use this signal as a run-time parameter.

csr_np[]

5

Output

Indicates the total number of bits per sample. The transport layer can use this signal as a run-time parameter.

csr_s[]

5

Output

Indicates the number of samples per converter per frame cycle. The transport layer can use this signal as a run-time parameter.

csr_hd

1

Output

Indicates the high density data format. The transport layer can use this signal as a run-time parameter.

csr_cf[]

5

Output

Indicates the number of control words per frame clock period per link. The transport layer can use this signal as a run-time parameter.

csr_lane_powerdown[]

L

Output

Indicates which lane is powered down. You need to set this signal if you have configured the link and want to reduce the number of active lanes.

Signal

Width

Direction

Description

Out-of-band (OOB)
jesd204_tx_int

1

Output

Interrupt pin for the JESD204B IP core. Interrupt is asserted when any error or synchronization request is detected. Configure the tx_err_enable register to set the type of error that can trigger an interrupt.

Signal

Width

Direction

Description

Debug or Testing
jesd204_tx_dlb_data[]

L*32

Output

Optional signal for parallel data from the DLL in TX to RX loopback testing. 31

jesd204_tx_dlb_kchar_data[]

L*4

Output

Optional signal to indicate the K character value for each byte in TX to RX loopback testing. 31

csr_tx_testmode[]

4

Output

Indicates the test mode for the JESD204B IP core and the test pattern for the test pattern generator in the design example.

Note: The test pattern generator is a component of the design example and is not a part of the JESD204B IP core.

Refer to the tx_test register in the register map.

csr_tx_testpattern_a[] 32 Output

A 32-bit fixed data pattern for testing purpose, such as short transport layer test pattern. You can configure the fixed data pattern through the TX register user_test_pattern_a (offset 0xD4)

32
csr_tx_testpattern_b[] 32 Output

A 32-bit fixed data pattern for testing purpose, such as short transport layer test pattern. You can configure the fixed data pattern through the TX register user_test_pattern_b (offset 0xD8)

32
csr_tx_testpattern_c[] 32 Output

A 32-bit fixed data pattern for testing purpose, such as short transport layer test pattern. You can configure the fixed data pattern through the TX register user_test_pattern_c (offset 0xDC)

32
csr_tx_testpattern_d[] 32 Output

A 32-bit fixed data pattern for testing purpose, such as short transport layer test pattern. You can configure the fixed data pattern through the TX register user_test_pattern_d (offset 0xE0)

32
30 The Transceiver PHY Reset Controller IP core controls this signal.
31 This signal is only for internal testing purposes. You can leave this signal disconnected.
32 You can connect this signal to the TX transport layer as test data samples or to the JESD204B TX IP core to emulate data from the TX transport layer. You may ignore this signal if unused.
Level Two Title