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1. Datasheet
2. Quick Start Guide
3. Intel® Arria® 10 or Intel® Cyclone® 10 GX Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Interrupts
8. Error Handling
9. PCI Express Protocol Stack
10. Transaction Layer Protocol (TLP) Details
11. Throughput Optimization
12. Design Implementation
13. Additional Features
14. Hard IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive
D. Document Revision History
1.1. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCI Express* Datasheet
1.2. Release Information
1.3. Device Family Support
1.4. Configurations
1.5. Debug Features
1.6. IP Core Verification
1.7. Resource Utilization
1.8. Recommended Speed Grades
1.9. Creating a Design for PCI Express
3.1. Parameters
3.2. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Settings
3.3. Base Address Register (BAR) and Expansion ROM Settings
3.4. Base and Limit Registers for Root Ports
3.5. Device Identification Registers
3.6. PCI Express and PCI Capabilities Parameters
3.7. Vendor Specific Extended Capability (VSEC)
3.8. Configuration, Debug, and Extension Options
3.9. PHY Characteristics
3.10. Example Designs
4.1. Hard IP Block Placement In Intel® Cyclone® 10 GX Devices
4.2. Hard IP Block Placement In Intel® Arria® 10 Devices
4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates
4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate
4.5. PCI Express Gen3 Bank Usage Restrictions
5.1. Clock Signals
5.2. Reset, Status, and Link Training Signals
5.3. ECRC Forwarding
5.4. Error Signals
5.5. Interrupts for Endpoints
5.6. Interrupts for Root Ports
5.7. Completion Side Band Signals
5.8. Parity Signals
5.9. LMI Signals
5.10. Transaction Layer Configuration Space Signals
5.11. Hard IP Reconfiguration Interface
5.12. Power Management Signals
5.13. Physical Layer Interface Signals
15.4.1. ebfm_barwr Procedure
15.4.2. ebfm_barwr_imm Procedure
15.4.3. ebfm_barrd_wait Procedure
15.4.4. ebfm_barrd_nowt Procedure
15.4.5. ebfm_cfgwr_imm_wait Procedure
15.4.6. ebfm_cfgwr_imm_nowt Procedure
15.4.7. ebfm_cfgrd_wait Procedure
15.4.8. ebfm_cfgrd_nowt Procedure
15.4.9. BFM Configuration Procedures
15.4.10. BFM Shared Memory Access Procedures
15.4.11. BFM Log and Message Procedures
15.4.12. Verilog HDL Formatting Functions
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9.2. Transaction Layer
The Transaction Layer is located between the Application Layer and the Data Link Layer. It generates and receives Transaction Layer Packets. The following illustrates the Transaction Layer. The Transaction Layer includes three sub-blocks: the TX datapath, Configuration Space, and RX datapath.
Tracing a transaction through the RX datapath includes the following steps:
- The Transaction Layer receives a TLP from the Data Link Layer.
- The Configuration Space determines whether the TLP is well formed and directs the packet based on traffic class (TC).
- TLPs are stored in a specific part of the RX buffer depending on the type of transaction (posted, non-posted, and completion).
- The TLP FIFO block stores the address of the buffered TLP.
- The receive reordering block reorders the queue of TLPs as needed, fetches the address of the highest priority TLP from the TLP FIFO block, and initiates the transfer of the TLP to the Application Layer.
- When ECRC generation and forwarding are enabled, the Transaction Layer forwards the ECRC DWORD to the Application Layer.
Tracing a transaction through the TX datapath involves the following steps:
- The Transaction Layer informs the Application Layer that sufficient flow control credits exist for a particular type of transaction using the TX credit signals. The Application Layer may choose to ignore this information.
- The Application Layer requests permission to transmit a TLP. The Application Layer must provide the transaction and must be prepared to provide the entire data payload in consecutive cycles.
- The Transaction Layer verifies that sufficient flow control credits exist and acknowledges or postpones the request. If there is insufficient space in the retry buffer, the Transaction Layer does not accept the TLP.
- The Transaction Layer forwards the TLP to the Data Link Layer.
Figure 59. Architecture of the Transaction Layer: Dedicated Receive Buffer