AN 846: Intel® Stratix® 10 Forward Error Correction

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ID 683805
Date 7/02/2018
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Necessity of Error Correction 3. FEC Selection 4. FEC in Intel® Stratix® 10 H-Tile Devices 5. FEC in Intel® Stratix® 10 E-Tile Devices 6. FEC Implementation Using the E-Tile Channel Placement Tool 7. FEC in Practical Application 8. Hardware Results 9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
2. Necessity of Error Correction x
2.1. Solutions to Transmission Errors 2.2. Error Correction Codes 2.3. What is FEC?
2.1. Solutions to Transmission Errors x
2.1.1. Parity and Cyclic Redundancy Check 2.1.2. Error Correction Code (ECC) Block Coding
2.3. What is FEC? x
2.3.1. FEC Definitions
3. FEC Selection x
3.1. Key Considerations when Choosing a FEC
4. FEC in Intel® Stratix® 10 H-Tile Devices x
4.1. Fire Code (802.3ap, 10GBASE-KR)
4.1. Fire Code (802.3ap, 10GBASE-KR) x
4.1.1. FEC Block Format 4.1.2. FEC Block Composition 4.1.3. FEC Sublayer for BASE-R PHYs 4.1.4. L-Tile/H-Tile Implementation
4.1.4. L-Tile/H-Tile Implementation x
4.1.4.1. Transcode Encoder 4.1.4.2. KR FEC Encoder 4.1.4.3. KR FEC Scrambler 4.1.4.4. KR FEC TX Gearbox 4.1.4.5. KR FEC RX Gearbox 4.1.4.6. Transcode Decoder
5. FEC in Intel® Stratix® 10 E-Tile Devices x
5.1. Types of RS-FEC 5.2. 100GBASE-KR4 5.3. 100GBASE-KP4 5.4. FEC Decoders 5.5. Specifications 5.6. Functions Within the RS-FEC Sublayer
5.1. Types of RS-FEC x
5.1.1. RS (528, 514, t = 7, m = 10) 5.1.2. RS (544, 514, t = 15, m = 10) 5.1.3. Supported RS-FEC Modes in E-Tile Devices
5.2. 100GBASE-KR4 x
5.2.1. 100GBASE-KR4 Mapping (IEEE802.3bj Clause 91)
5.3. 100GBASE-KP4 x
5.3.1. 100GBASE-KP4 Mapping (IEEE802.3bj Clause 91)
5.6. Functions Within the RS-FEC Sublayer x
5.6.1. Lane Block Synchronization 5.6.2. Alignment Lock and Deskew 5.6.3. Lane Re-order 5.6.4. Alignment Marker Removal 5.6.5. 64B/66B to 256B/257B Transcoder
7. FEC in Practical Application x
7.1. Datacenter Applications Scenario
8. Hardware Results x
8.1. Test Design 8.2. Test Setup 8.3. Insertion Loss Plots 8.4. FEC Statistics Tool 8.5. Hardware Data 8.6. Comparison to the Specification 8.7. References
1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction

5.1.3. Supported RS-FEC Modes in E-Tile Devices

The RS-FEC core supports the client types in the following table.
Table 6.  Client Types and Attributes
Client Type FEC Code Number of Physical Lanes Marker Size (bits) Synchronization Type
100GbE RS528 4 1285 AM
100GbE with KP-FEC RS544 2 1285 AM
128GFC RS528 4 514 AM
25GbE RS528 1 257 CWM
32GFC RS528 1 — SnT

Legend:

  • RS528 = RS(528, 514)
  • RS544 = RS(544, 514)
  • AM = Alignment Markers
  • CWM = Codeword Marker
  • SnT = Scramble-and-Test

The RS-FEC core supports the following standards:

  • 100GbE: IEEE 802.3 Clause 91
  • 100GbE with KP-FEC: IEEE 802.3 Clause 91
  • 128GFC: Fibre Channel Framing and Signaling - 4 (FC-FCS-4) Clause 5.6
  • 25GbE: IEEE 802.3 Clause 108
  • 32GFC: Fibre Channel Framing and Signaling - 4 (FC-FCS-4) Clause 5.4

100GbE with KP-FEC uses two physical PAM4 coded lanes, also called, 100 Gigabit Attachment Unit Interface (CAUI-2). It uses the RS(544,514). The two physical lanes are supported by bit-multiplexing the RS-FEC Core’s four PMA lanes pairwise outside of the RS-FEC Core. The remaining defined clients use the RS(528,514) FEC.

In the CPRI standard, the CPRI FEC refers to 32GFC. CPRI is like 32GFC except for the line rate, which is 24 Gbps.

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