Visible to Intel only — GUID: vud1488511313928
Ixiasoft
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
DLL Range Specifications
DQS Logic Block Specifications
Memory Output Clock Jitter Specifications
OCT Calibration Block Specifications
POR Specifications
JTAG Configuration Timing
FPP Configuration Timing
AS Configuration Timing
DCLK Frequency Specification in the AS Configuration Scheme
PS Configuration Timing
Initialization
Configuration Files
Minimum Configuration Time Estimation
Remote System Upgrades
User Watchdog Internal Circuitry Timing Specifications
Visible to Intel only — GUID: vud1488511313928
Ixiasoft
JTAG Configuration Timing
Symbol | Description | Min | Max | Unit |
---|---|---|---|---|
tJCP | TCK clock period | 30, 167 70 | — | ns |
tJCH | TCK clock high time | 14 | — | ns |
tJCL | TCK clock low time | 14 | — | ns |
tJPSU (TDI) | TDI JTAG port setup time | 2 | — | ns |
tJPSU (TMS) | TMS JTAG port setup time | 3 | — | ns |
tJPH | JTAG port hold time | 5 | — | ns |
tJPCO | JTAG port clock to output | — | 11 | ns |
tJPZX | JTAG port high impedance to valid output | — | 14 | ns |
tJPXZ | JTAG port valid output to high impedance | — | 14 | ns |
70 The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.