Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

ID 683871
Date 9/01/2020
Public
Document Table of Contents

4.3.10. Correctable Internal Error Status Register

This register reports the status of the internally checked errors that are correctable. When these specific errors are enabled by the Correctable Internal Error Mask register, they are forwarded as Correctable Internal Errors as defined in the PCI Express Base Specification 3.0. This register is for debug only. Use this register to observe behavior, not to drive custom logic.

Table 16.  Correctable Internal Error Status Register (Byte Offset: 0x23C)
Bits Reset Value Access Description
[31:7] 0x000 RO Reserved.
[6] 1'b0 RW1CS A value of 1 indicates that the Application Layer has detected a correctable internal error.
[5] 1'b0 RW1CS A value of 1 indicates a configuration error has been detected in CvP mode, which is reported as correctable. This bit is set whenever a CVP_CONFIG_ERROR occurs while in CVP_MODE.
[4:2] 0x0 RO Reserved.
[1] 1'b0 RW1CS A value of 1 indicates a retry buffer correctable ECC error.
[0] 1'b0 RW1CS A value of 1 indicates an RX buffer correctable ECC error.