HDMI PHY Intel FPGA IP Design Example User Guide

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ID 732781
Date 7/20/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI PHY Design Example Quick Start Guide for Intel® Arria® 10 Devices 2. HDMI 2.0 PHY Design Example 3. Document Revision History for the HDMI PHY Intel FPGA IP Design Example User Guide
1. HDMI PHY Design Example Quick Start Guide for Intel® Arria® 10 Devices x
1.1. Generating the Design 1.2. Compiling and Testing the Design 1.3. HDMI PHY Intel® FPGA IP Design Example Parameters
2. HDMI 2.0 PHY Design Example x
2.1. Hardware and Software Requirements 2.2. Directory Structure 2.3. Reconfiguration Sequence Flow 2.4. Interface Signals 2.5. Clocking Scheme 2.6. Hardware Setup
2.1. Hardware and Software Requirements x
2.1.1. Hardware 2.1.2. Software
1. HDMI PHY Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.0 PHY Design Example
3. Document Revision History for the HDMI PHY Intel FPGA IP Design Example User Guide

1.2. Compiling and Testing the Design

To compile and run a demonstration test on the hardware example design, follow these steps:
  1. Ensure hardware example design generation is complete.
  2. Launch the Intel® Quartus® Prime software and open the .qpf file: <Design Example>/quartus/a10_hdmi2_demo.qpf
  3. Click Processing > Start Compilation.
  4. After successful compilation, a .sof file is generated in the quartus/output_files directory.
  5. Connect Bitec HDMI 2.0 FMC Daughter Card Rev 11 to the on-board FMC port B (J2).
  6. Connect TX (P1) of the Bitec FMC daughter card to an external video source.
  7. Connect RX (P2) of the Bitec FMC daughter card to an external video sink or video analyzer.
  8. Ensure all switches on the development board are in default position.
  9. Configure the selected Intel® Arria® 10 device on the development board using the generated .sof file (Tools > Programmer).
  10. The analyzer should display the video generated from the source.
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