Embedded Peripherals IP User Guide

ID 683130
Date 2/16/2024
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

30.1. Core Overview

The direct memory access (DMA) controller core with Avalon® interface performs bulk data transfers, reading data from a source address range and writing the data to a different address range. An Avalon® Memory-Mapped ( Avalon® -MM) host peripheral, such as a CPU, can offload memory transfer tasks to the DMA controller. While the DMA controller performs memory transfers, the host is free to perform other tasks in parallel.

The DMA controller transfers data as efficiently as possible, reading and writing data at the maximum pace allowed by the source or destination. The DMA controller is capable of performing Avalon® transfers with flow control, enabling it to automatically transfer data to or from a slow peripheral with flow control (for example, UART), at the maximum pace allowed by the peripheral.

Instantiating the DMA controller in Platform Designer creates one agent port and two host ports. You must specify which agent peripherals can be accessed by the read and write host ports. Likewise, you must specify which other host peripheral(s) can access the DMA control port and initiate DMA transactions. The DMA controller does not export any signals to the top level of the system module.
Note: While instantiating the DMA controller in the hierarchical subsystem, add an Avalon® -MM pipeline bridge in front of the exported host interface of the DMA controller in the subsystem. This will allow you to configure the bus width of the pipeline bridge to match the agent address bus.

For the Nios® II and Nios® V processors, device drivers are provided in the HAL system library. See the Software Programming Model section for details of HAL support.