FFT IP Core: User Guide

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ID 683374
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. FFT IP Core Getting Started 3. FFT IP Core Functional Description 4. Block Floating Point Scaling 5. Document Revision History A. FFT IP Core User Guide Document Archive
1. About This IP Core x
1.1. Intel® DSP IP Core Features 1.2. FFT IP Core Features 1.3. General Description 1.4. DSP IP Core Device Family Support 1.5. DSP IP Core Verification 1.6. FFT IP Core Release Information 1.7. Performance and Resource Utilization
1.3. General Description x
1.3.1. Fixed Transform Size FFT 1.3.2. Variable Streaming FFT
2. FFT IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.5. Simulating Intel® FPGA IP Cores 2.6. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. FFT IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.4. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) x
2.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.5. Simulating Intel® FPGA IP Cores x
2.5.1. Simulating the Fixed-Transform FFT IP Core in the MATLAB Software 2.5.2. Simulating the Variable Streaming FFT IP Core in the MATLAB Software
3. FFT IP Core Functional Description x
3.1. Fixed Transform FFTs 3.2. Variable Streaming FFTs 3.3. FFT Processor Engines 3.4. I/O Data Flow 3.5. FFT IP Core Parameters 3.6. FFT IP Core Interfaces and Signals
3.2. Variable Streaming FFTs x
3.2.1. Fixed-Point Variable Streaming FFTs 3.2.2. Floating-Point Variable Streaming FFTs
3.3. FFT Processor Engines x
3.3.1. Quad-Output FFT Engine 3.3.2. Single-Output FFT Engine
3.4. I/O Data Flow x
3.4.1. Streaming FFT 3.4.2. Variable Streaming 3.4.3. Buffered Burst 3.4.4. Burst
3.4.1. Streaming FFT x
3.4.1.1. Using the Streaming FFT 3.4.1.2. Changing the Direction on a Block-by-Block Basis 3.4.1.3. Enabling the Streaming FFT
3.4.2. Variable Streaming x
3.4.2.1. Changing Block Size 3.4.2.2. Changing Direction 3.4.2.3. I/O Order 3.4.2.4. Enabling the Variable Streaming FFT 3.4.2.5. Dynamically Changing the FFT Size 3.4.2.6. I/O Order
3.4.3. Buffered Burst x
3.4.3.1. Enabling the Buffered Burst FFT
3.6. FFT IP Core Interfaces and Signals x
3.6.1. Avalon-ST Interfaces in DSP IP Cores 3.6.2. FFT IP Core Avalon-ST Signals
3.6.2. FFT IP Core Avalon-ST Signals x
3.6.2.1. Component Specific Signals
4. Block Floating Point Scaling x
4.1. Possible Exponent Values 4.2. Implementing Scaling 4.3. Unity Gain in an IFFT+FFT Pair
4.2. Implementing Scaling x
4.2.1. Example of Scaling
1. About This IP Core
2. FFT IP Core Getting Started
3. FFT IP Core Functional Description
4. Block Floating Point Scaling
5. Document Revision History
A. FFT IP Core User Guide Document Archive

5. Document Revision History

FFT IP Core User Guide revision history.
Date Version Changes Made
2017.11.06 17.1
  • Added support for Intel® Cyclone® 10 devices.
  • Removed bit-reversed option.
  • Removed input and output orders topic.
2017.01.14 16.1.1
  • Removed DC centred option from variable streaming input and output option orders.
  • Removed product ID and vendor ID codes.
2016.11.11 16.1 Added note about fftpts signal.
2016.08.01 16.1S10 Added support for Stratix 10 devices
2016.05.01 16.0 Added MATLAB simulation flow.
2015.10.01 15.1 Added more info to sink_data and source_data signals
2014.12.15 14.1
  • Added more detail to source_data and sink_data signal descriptions.
  • Added hard-floating point option for Arria 10 devices in the Complex Multiplier Options
  • Reworded DSP Block Resource Optimization description
  • Added block floating point option in parameters table.
  • Reordered parameters in parameters table.
  • Removed the following parameters:
    • Twiddle ROM Distribution
    • Use M-RAM or M144K blocks
    • Implement appropriate logic functions in RAM
    • Structure
    • Implement Multipliers in
    • Global enable clock signal
  • Removed Stratix V devices only comment for DSP Resource Optimization parameter.
  • Added final support for Arria 10 and MAX 10 devices
August 2014 14.0 Arria 10 Edition
  • Added support for Arria 10 devices.
  • Added new source_data bus description.
  • Added Arria 10 generated files description.
  • Removed table with generated file descriptions.
  • Removed clk_ena
June 2014 14.0
  • Removed Cyclone III and Stratix III device support
  • Added support for MAX 10 FPGAs.
  • Added instructions for using IP Catalog
November 2013 13.1
  • Added more information to variable streaming I/O dataflow.
  • Removed device support for following devices:
    • HardCopy II, HardCopy III, HardCopy IV E, HardCopy IV GX
    • Stratix, Stratix GX, Stratix II, Stratix II GX
    • Cyclone, Cyclone II
    • Arria GX
November 2012 12.1 Added support for Arria V GZ devices.
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