FFT IP Core: User Guide

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ID 683374
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. FFT IP Core Getting Started 3. FFT IP Core Functional Description 4. Block Floating Point Scaling 5. Document Revision History A. FFT IP Core User Guide Document Archive
1. About This IP Core x
1.1. Intel® DSP IP Core Features 1.2. FFT IP Core Features 1.3. General Description 1.4. DSP IP Core Device Family Support 1.5. DSP IP Core Verification 1.6. FFT IP Core Release Information 1.7. Performance and Resource Utilization
1.3. General Description x
1.3.1. Fixed Transform Size FFT 1.3.2. Variable Streaming FFT
2. FFT IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.5. Simulating Intel® FPGA IP Cores 2.6. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. FFT IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.4. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) x
2.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.5. Simulating Intel® FPGA IP Cores x
2.5.1. Simulating the Fixed-Transform FFT IP Core in the MATLAB Software 2.5.2. Simulating the Variable Streaming FFT IP Core in the MATLAB Software
3. FFT IP Core Functional Description x
3.1. Fixed Transform FFTs 3.2. Variable Streaming FFTs 3.3. FFT Processor Engines 3.4. I/O Data Flow 3.5. FFT IP Core Parameters 3.6. FFT IP Core Interfaces and Signals
3.2. Variable Streaming FFTs x
3.2.1. Fixed-Point Variable Streaming FFTs 3.2.2. Floating-Point Variable Streaming FFTs
3.3. FFT Processor Engines x
3.3.1. Quad-Output FFT Engine 3.3.2. Single-Output FFT Engine
3.4. I/O Data Flow x
3.4.1. Streaming FFT 3.4.2. Variable Streaming 3.4.3. Buffered Burst 3.4.4. Burst
3.4.1. Streaming FFT x
3.4.1.1. Using the Streaming FFT 3.4.1.2. Changing the Direction on a Block-by-Block Basis 3.4.1.3. Enabling the Streaming FFT
3.4.2. Variable Streaming x
3.4.2.1. Changing Block Size 3.4.2.2. Changing Direction 3.4.2.3. I/O Order 3.4.2.4. Enabling the Variable Streaming FFT 3.4.2.5. Dynamically Changing the FFT Size 3.4.2.6. I/O Order
3.4.3. Buffered Burst x
3.4.3.1. Enabling the Buffered Burst FFT
3.6. FFT IP Core Interfaces and Signals x
3.6.1. Avalon-ST Interfaces in DSP IP Cores 3.6.2. FFT IP Core Avalon-ST Signals
3.6.2. FFT IP Core Avalon-ST Signals x
3.6.2.1. Component Specific Signals
4. Block Floating Point Scaling x
4.1. Possible Exponent Values 4.2. Implementing Scaling 4.3. Unity Gain in an IFFT+FFT Pair
4.2. Implementing Scaling x
4.2.1. Example of Scaling
1. About This IP Core
2. FFT IP Core Getting Started
3. FFT IP Core Functional Description
4. Block Floating Point Scaling
5. Document Revision History
A. FFT IP Core User Guide Document Archive

4.3. Unity Gain in an IFFT+FFT Pair

Given sufficiently high precision, such as with floating-point arithmetic, in theory you can obtain unity gain when you cascade an IFFT and FFT. However, in BFP arithmetic, pay special attention to the exponent values of the IFFT/FFT blocks to achieve the unity gain. This section explains the steps to derive a unity gain output from an IFFT/FFT IP Core pair, using BFP arithmetic.

BFP arithmetic does not provide an input for the exponent, so you must keep track of the exponent from the IFFT block if you are feeding the output to the FFT block immediately thereafter and divide by N at the end to acquire the original signal magnitude.

Figure 21. Derivation to Achieve IFFT/FFT Pair Unity Gain

where:

x0 = Input data to IFFT

X0 = Output data from IFFT

N = number of points

data1 = IFFT output data and FFT input data

data2 = FFT output data

exp1 = IFFT output exponent

exp2 = FFT output exponent

IFFTa = IFFT

FFTa = FFT

Any scaling operation on X0 followed by truncation loses the value of exp1 and does not result in unity gain at x0. Any scaling operation must be done on X0 only when it is the final result. If the intermediate result X0 is first padded with exp1 number of zeros and then truncated or if the data bits of X0 are truncated, the scaling information is lost.

To keep unity gain, you can pas the exp1 value to the output of the FFT block. Alternatively, preserve the full precision of data1×2–exp1 and use this value as input to the FFT block. The second method requires a large size for the FFT to accept the input with growing bit width from IFFT operations. The resolution required to accommodate this bit width in most cases, exceeds the maximum data width supported by the IP core.

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