Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 8/16/2022
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Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Avalon®-MM in Remote Update Intel® FPGA IP Core 1.2. Intel Arria 10 and Intel Cyclone® 10 GX Devices 1.3. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.4. Cyclone IV and Intel Cyclone 10 LP Devices 1.5. Flash Memory Programming Files 1.6. Design Examples 1.7. Remote Update Intel® FPGA IP User Guide Archives 1.8. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.2. Intel Arria 10 and Intel Cyclone® 10 GX Devices x
1.2.1. Remote System Configuration Mode 1.2.2. Remote System Configuration Components 1.2.3. Parameter Settings 1.2.4. Ports 1.2.5. Parameters 1.2.6. Avalon-MM Interface 1.2.7. Enabling Remote System Upgrade Circuitry 1.2.8. Generating Initial RSU Image
1.2.1. Remote System Configuration Mode x
1.2.1.1. Remote System Upgrade State Machine
1.2.1.1. Remote System Upgrade State Machine x
1.2.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.2.6. Avalon-MM Interface x
1.2.6.1. Control Status Register Signals 1.2.6.2. Register Map
1.2.6.1. Control Status Register Signals x
1.2.6.1.1. Control Status Register Write Operation 1.2.6.1.2. Control Status Register Read Operation 1.2.6.1.3. Operations Example Waveforms
1.3. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon-MM Interface 1.3.7. Enabling Remote System Upgrade Circuitry
1.3.6. Avalon-MM Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation
1.4. Cyclone IV and Intel Cyclone 10 LP Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Remote Update Operation 1.4.7. Avalon-MM Interface 1.4.8. Enabling Remote System Upgrade Circuitry
1.4.7. Avalon-MM Interface x
1.4.7.1. Control Status Register Signals 1.4.7.2. Register Map 1.4.7.3. Read Source Mapping
1.4.7.1. Control Status Register Signals x
1.4.7.1.1. Control Status Register Write Operation 1.4.7.1.2. Control Status Register Read Operation
1.6. Design Examples x
1.6.1. Intel Arria 10 Remote Update Design Example 1.6.2. Cyclone V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.3.6.1. Control Status Register Signals

Table 11.  Remote Update Intel® FPGA IP Core Avalon® -MM Control Status Register Signals for Arria® II, Arria® V, Cyclone® V, Stratix® IV, and Stratix® V Devices
Name Width Direction Description
clk 1 Input Clock input.
reset 1 Input Reset input.
avl_csr_address 3 Input Address bus.
avl_csr_read 1 Input Perform a read transaction.
avl_csr_write 1 Input Perform a write transaction.
avl_csr_readdata 32 Output Read data from IP.
avl_csr_readdata_valid 1 Output Indicate when read data is valid.
avl_csr_writedata 32 Input Write data to IP.
avl_csr_waitrequest 1 Output Waitrequest signal high indicates the core is busy.

Section Content
Control Status Register Write Operation
Control Status Register Read Operation

Level Two Title