PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.2.3. Input Path Signals

Table 44.  Input Path SignalsInput path signals are signals that are available when you set the Pin Type parameter to Input or Bidirectional. The <n> in the signal names below represents the group number in the IP.
Signal Name Direction Width Description
group_<n>_data_to_core Output

Quarter-rate DDR: 8 x PIN_WIDTH

Half-rate DDR: 4 x PIN_WIDTH

Full-rate DDR: 2 x PIN_WIDTH

Quarter-rate SDR: 4 x PIN_WIDTH

Half-rate SDR: 2 x PIN_WIDTH

Full-rate SDR: 1 x PIN_WIDTH

Output data to the core logic. Valid on rdata_valid. Synchronous to the core_clk output from the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP.
group_<n>_rdata_en Input

Quarter-rate: 4

Half-rate: 2

Full-rate: 1

This signal represents the number of expected words to read from the external device.

This signal is set to high after a read command is issued. Synchronous to the core_clk output from the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP.

When using the IP as a receiver, assert this signal after interface_locked signal is asserted and strobe_in is stable.

group_<n>_rdata_valid Output

Quarter-rate: 4

Half-rate: 2

Full-rate: 1

This signal determines which data are valid when reading from Read FIFO. Delayed by READ_LATENCY with margin and aligned to the core clock rate. For example, in quarter-rate, the delay is a multiple of 4 external clock cycles.

Synchronous to the core_clk output from the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP.

group_<n>_data_in/

group_<n>_data_io

Input/Bidirectional

1 to 48 if data configuration is Single Ended

Input and output data from/to external device. Synchronous to the group_<n>_strobe_in or group_<n>_strobe_io input. The first data_in must be associated with positive edge of strobe_in/strobe_io.

If the pin type is set to Input, the data_in ports are used. If the pin type is set to bidirectional, the data_io ports are used.

Note: PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP does not support differential data pins.
group_<n>_strobe_in/group_<n>_strobe_io Input/Bidirectional 1

Input and output strobe from/to external device. If the pin type is set to Input, the group_<n>_strobe_in signal is used. If the pin type is set to Bidirectional, the group_<n>_strobe_io signal is used.

group_<n>_strobe_in_n group_<n>_strobe_io_n Input/Bidirectional 1 Negative strobe from/to external device. This is used if the Strobe Configuration parameter is set to Differential or Complementary. If the pin type is set to Input, the strobe_in_n signal is used. If the pin type is set to Bidirectional, the strobe_io_n signal is used.