AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

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ID 683731
Date 1/30/2018
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Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link

Perform the following steps to execute the software C code and initialize the JESD204B link:

  1. After device programming, navigate to the Tools menu and select Nios II Software Build Tools for Eclipse.
  2. In the Select a workspace dialog box, navigate to the software workspace, <project directory>/software and click OK.
  3. To import the software project into Eclipse, right click in the project explorer window and select Import.
  4. Under the general category select Existing Projects into Workspace and click Next.
  5. Select archive file and navigate to the zip file of interest. Click Finish and the project will be setup in your workspace.
  6. To download the executable code to the development board, right click on the jesd204b_nios2_ed in Project Explorer window and select Run As and select Nios II Hardware.
    Click Yes if a dialog box stating "Errors exist in required project. Continue to launch." appears.

    The C codes need to be recompiled if you want to test other supported pattern or internal serial loopback. In this case, you must regenerate the BSP files. In the Project Explorer window, right click the jesd204b_nios2_ed_bsp project, navigate to Nios® II and click Generate BSP. This regenerates the BSP files based on your current jesd204b_ed_qsys.sopcinfo. Refer to Table 3 to change related software parameters.

    Note: Follow steps in Reconstructing Design and Running in Hardware to rebuild the Nios® II project if you recompile your project or the project doesn’t work.
The code performs the JESD204B link initialization sequence and exits after successful download the .elf file. You can view the code execution results on the Nios® II Console tab. The following tables list the expected values of the link status register for each JESD204B IP core.
Table 1.  TX Status 0 Registers Bits
Bit Name Description Expected Binary Value
[0] SYNC_N Value

0: Receiver is not in sync

1: Link is in sync

 1
[2:1] Data Link Layer (DLL) State

00: Code Group Synchronization (CGS)

01: Initial Lane Alignment Sequences

10: User Data Mode

11: D21.5 test mode

 10
Table 2.  RX Status 0 Registers Bits
Bit Name Description Expected Binary Value
[0] SYNC_N Value

0: Receiver is not in sync

1: Link is in sync

 1
Others - - Don’t Care
Note: You can refer to reconstruct design section if you want to rebuilt the Intel® Quartus® Prime and Nios® II project before running in the hardware.
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