AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

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ID 683731
Date 1/30/2018
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Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.2.3. Software Parameters

The software parameters defined in the main header file (main.h) controls various behaviors of the C code.
Table 3.  Software Parameters
Parameter Default Value Description
DEBUG_MODE 0 Set to 1 to print debug messages, else set to 0.
PRINT_INTERRUPT_MESSAGES 1 Set to 1 to print JESD204B error interrupt messages, else set to 0.
PATCHK_EN 1 Set to 1 when test pattern checker is included in the initial design data path configuration, else set to 0.
DATAPATH 3

Set to indicate the JESD204B IP configurations:

  • 1: TX data path only
  • 2: RX data path only
  • 3: Duplex data path (TX and RX data path)
MAX_LINKS 1

Set to 1 in this design to indicate a JESD204B subsystem that contains two JESD204B IP cores instances.1

MAX_INSTANCES 2

Set to indicate the number of instances in a JESD204B subsystem. Set to 2 in this design to indicate 2 JESD204B instances per subsystem.2

LOOPBACK_INIT 0 Initial value of the loopback. Set to 1 for internal serial loopback mode, else set to 0.
SOURCEDEST_INIT PRBS

Initial value of source/destination. Set to indicate test pattern generator or checker type or user mode:

  • USER: User mode (no test pattern generator or checker in data path).
  • ALT: Test pattern generator or checker set in alternate checkerboard mode.
  • RAMP: Test pattern generator or checker set in ramp wave mode.
  • PRBS: Test pattern generator or checker set in parallel PRBS mode.
1 The maximum supported values of MAX_LINKS are 1 for two JESD204B IP instances in a subsystem. You may need to modify Nios® II C code and Platform Designer base addresses space if more than 4 JESD204B IP instances in a JESD204B subsystem or multiple JESD204B subsystem.
2 The maximum supported value of MAX_INSTANCES is 2. You can add up to 4 JESD204B IP cores instances per subsystem without modifying the address space, but you need to modify the Nios® II C code.
Level Two Title