Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.3.9.1. PR Control Block Signal Timing Diagrams

Successful PR Session ( Intel® Arria® 10 Example)

The following flow describes a successful Intel® Arria® 10 PR session:

  1. Assert PR_REQUEST and wait for PR_READY; drive PR_DATA to 0.
  2. The PR control block asserts PR_READY, asynchronous to clk.
  3. Start sending Raw Binary File (.rbf) to the PR control block, with 1 valid word per clock cycle. On .rbf file transfer completion, drive PR_DATA to 0. The PR control block asynchronously asserts PR_DONE when the control block completes the reconfiguration operation. The PR control block deasserts PR_READY on configuration completion.
  4. Deassert PR_REQUEST. The PR control block acknowledges the end of PR_REQUEST, and deasserts PR_DONE. The host can now initiate another PR session.
Figure 58. Timing Diagram for Successful Intel® Arria® 10 PR Session

Unsuccessful PR Session with Configuration Frame Readback Error ( Intel Arria 10 Example)

The following flow describes an Intel® Arria® 10 PR session with error in the EDCRC verification of a configuration frame readback:
  1. The PR control block internally detects a CRC error.
  2. The CRC control block then asserts CRC_ERROR.
  3. The PR control block asserts the PR_ERROR.
  4. The PR control block deasserts PR_READY, so that the host can withdraw the PR_REQUEST.
  5. The PR control block deasserts CRC_ERROR and clears the internal CRC_ERROR signal to get ready for a new PR session. The host can now initiate another PR session.
Figure 59. Timing Diagram for Unsuccessful Intel® Arria® 10 PR Session with Configuration Frame Readback Error

Unsuccessful PR Session with PR_ERROR ( Intel Arria 10 Example)

The following flow describes an Intel® Arria® 10 PR session with transmission error or configuration CRC error:

  1. The PR control block asserts PR_ERROR.
  2. The PR control block deasserts PR_READY, so that the host can withdraw PR_REQUEST.
  3. The PR control block deasserts PR_ERROR to get ready for a new PR session. The host can now initiate another PR session.
Figure 60. Timing Diagram for Unsuccessful Intel® Arria® 10 PR Session with PR_ERROR

Late Withdrawal PR Session ( Intel Arria 10 Example)

The following flow describes a late withdrawal Intel® Arria® 10 PR session:

  1. The PR host can withdraw the request after the PR control block asserts PR_READY.
  2. The PR control block deasserts PR_READY. The host can now initiate another PR session.
Figure 61. Timing Diagram for Late Withdrawal Intel® Arria® 10 PR Session
Note: The PR host can withdraw the request any time before the PR controller asserts PR_READY. Therefore, the PR host must not return until the PR control block asserts PR_READY. Provide at least 10 PR_CLK cycles after deassertion of PR_REQUEST, before requesting a new PR session.