F-Tile SDI II FPGA IP Design Example User Guide

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ID 710496
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Component
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description 2.4.3. Hardware Testing 2.4.4. Signal
2.4.3. Hardware Testing x
2.4.3.1. Parallel loopback 2.4.3.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

1.4. Compiling and Testing the Design in Hardware

Figure 8. Compiling and Testing the Design Flow
To compile and run a demonstration test on the hardware design example, follow these steps:
  1. Open the Intel® Quartus® Prime project (sdi_ii_agi_demo.qpf) located in Quartus directory.
  2. To perform Intel® Quartus® Prime compilation, click Processing > Start Compilation.
  3. Connects the Nextera SDI daughter card to FMC port A on the development kit.
  4. For parallel loopback design, connects the BNC RX connector (J1/12G In) to an external video source and connects the TX connector (J2/12G Out) to a video analyzer. For serial loopback design, connects the BNC TX connector (J2/12G Out) to RX connector (J1/12G In) or a video analyzer.
  5. Ensure all the switches on the development kit are in their default position.

    If you are generating parallel loopback without external VCXO design example, or you have enabled the Dynamic Tx clock switching parameter, toggle DIPSW S22.3 onboard to OFF position

  6. Open Clock Controller GUI and navigate to Si5391-A tab, set Out9 frequency to:
    • Parallel loopback without external VCXO – 140.00000 MHz
    • Dynamic Tx clock switching is enabled – 148.35160 MHz
    Figure 9. Setting Out9 frequency in Clock Controller
  7. After the compilation completes, open Programmer and program the generated .sof file to the development kit.
  8. For serial loopback design, you need to open System Console to control the internal video pattern generator.
    1. Go to Tools > System Debugging Tools and click System Console.
    2. After the initialization, type source ../hwtest/tpg_ctrl.tcl to open the pattern generator control UI.
    3. Select your desired video format through the UI.
    Note: To allow segmented frame video format (1080sF30, 1080sF25) and interlaced video format (1080i60, 1080i50) to be correctly differentiated in external analyzer, you must insert Payload ID in the serial loopback design
    Figure 10. Selecting Video Format Through System Console
  9. The analyzer should be able to display the video generated from the source. Refer to jumper settings in the Jumper Settings and Descriptions Table to change the jumper (J8) position before switching between fractional frame rate and integer frame rate video format. You must press the push button (PB0) to trigger a device (LMK03328) power cycling through the PDN pin every time you change the jumper (J8) position.
    Figure 11. Jumper Settings on Nextera 12G-SDI FMC Daughtercard
Table 3.  Jumper Settings and Descriptions
Jumper Block Description Setting
J7 Programming Header -
J8

To switch the generated clock frequency to TX channel:

  • Pin 1-2 = 297 Mhz
  • Pin 2-3 = 297/1.001 Mhz
 1-2: 297 Mhz

2-3: 297/1.001 Mhz
J9

To select SDI or IP mode:

  • Pin 1-2 = SDI mode
  • Pin 2-3 = IP mode
 1-2
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