F-Tile SDI II FPGA IP Design Example User Guide

ID 710496
Date 4/04/2022
Public

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2.1. Features

  1. LED status for early debugging stage with RX or TX only options.
  2. To use RX or TX only components, remove the irrelevant blocks from the simplex version serial loopback design as described in the following table.
    Table 5.  Features
    User Require Preserve Remove
    RX only
    • RX top
    • Reference and System PLL Clocks IP
    • DR IP & DR arbiter (if present)
    • Device Init
    TX Top
    TX only
    • TX top
    • Reference and System PLL Clocks IP
    • DR IP & DR arbiter (if present)
    • Device Init
    RX Top
Figure 12. Components required for TX or RX only design on Intel® Agilex™ Device
Note:
  • Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
  • (1)Block/Connection only required for triple rate/multi rate designs.
  • (2)Multiple copies of block are required for different PHY profiles in triple rate/multi rate designs.