F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 1/26/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

A.2.2.4.2. ACS Capability Register (Offset 0x4)

Table 139.  ACS Capability Register
Bits Register Description Default Value Access
[31:0] Capability Field 0x0 RO