F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 1/26/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.1.1.3. Additional Debug Tools

Use the Hard IP reconfiguration interface and PHY reconfiguration interface on the F-Tile Avalon® -ST IP for PCI Express to access additional registers (for example, receiver detection, lane reversal etc.).

Figure 79. Register Access for Debug