External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3.4. AFI Calibration Status Timing Diagram

The controller interacts with the PHY during calibration at power-up and at recalibration.

At power-up, the PHY holds afi_cal_success and afi_cal_fail 0 until calibration is done, when it asserts afi_cal_success, indicating to controller that the PHY is ready to use and afi_wlat and afi_rlat signals have valid values.

At recalibration, the controller asserts afi_cal_req, which triggers the same sequence as at power-up, and forces recalibration of the PHY.

Figure 96. Calibration