External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.1.8. status for DDR4

PHY calibration status interface
Table 21.  Interface: statusInterface type: Conduit
Port Name Direction Description
local_cal_success Output When high, indicates that PHY calibration was successful
local_cal_fail Output When high, indicates that PHY calibration failed