Nios II Custom Instruction User Guide

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ID 683242
Date 4/27/2020
Public
Document Table of Contents
Document Table of Contents x
1. Nios II Custom Instruction Overview 2. Custom Instruction Hardware Interface 3. Custom Instruction Software Interface 4. Design Example: Cyclic Redundancy Check 5. Introduction to Nios® II Floating Point Custom Instructions 6. Nios II Floating Point Hardware 2 Component 7. Nios® II Floating Point Hardware (FPH1) Component 8. Document Revision History for Nios II Custom Instruction User Guide
1. Nios II Custom Instruction Overview x
1.1. Custom Instruction Implementation
1.1. Custom Instruction Implementation x
1.1.1. Custom Instruction Hardware Implementation 1.1.2. Custom Instruction Software Implementation
2. Custom Instruction Hardware Interface x
2.1. Custom Instruction Types
2.1. Custom Instruction Types x
2.1.1. Combinational Custom Instructions 2.1.2. Multicycle Custom Instructions 2.1.3. Extended Custom Instructions 2.1.4. Internal Register File Custom Instructions 2.1.5. External Interface Custom Instructions
2.1.1. Combinational Custom Instructions x
2.1.1.1. Combinational Custom Instruction Ports 2.1.1.2. Combinational Custom Instruction Timing
2.1.2. Multicycle Custom Instructions x
2.1.2.1. Multicycle Custom Instruction Ports 2.1.2.2. Multicycle Custom Instruction Timing
2.1.3. Extended Custom Instructions x
2.1.3.1. Extended Custom Instruction Timing
2.1.4. Internal Register File Custom Instructions x
2.1.4.1. Internal Register File Custom Instruction Example 2.1.4.2. Internal Register File Custom Instruction Ports
3. Custom Instruction Software Interface x
3.1. Custom Instruction Software Examples 3.2. Built-in Functions and User-defined Macros 3.3. Custom Instruction Assembly Language Interface
3.2. Built-in Functions and User-defined Macros x
3.2.1. Built-in Functions with No Return Value 3.2.2. Built-in Functions that Return a Value of Type Int 3.2.3. Built-in Functions that Return a Value of Type Float 3.2.4. Built-in Functions that Return a Pointer Value
3.3. Custom Instruction Assembly Language Interface x
3.3.1. Custom Instruction Assembly Language Syntax 3.3.2. Custom Instruction Assembly Language Examples 3.3.3. Custom Instruction Word Format
3.3.3. Custom Instruction Word Format x
3.3.3.1. Select Index Field (N)
4. Design Example: Cyclic Redundancy Check x
4.1. Building the CRC Example Hardware 4.2. Building the CRC Example Software
4.1. Building the CRC Example Hardware x
4.1.1. Setting up the Environment for the CRC Example Design 4.1.2. Opening the Component Editor 4.1.3. Specifying the Custom Instruction Component Type 4.1.4. Displaying the Custom Instruction Block Symbol 4.1.5. Adding the CRC Custom Instruction HDL Files 4.1.6. Configuring the Custom Instruction Parameter Type 4.1.7. Setting Up the CRC Custom Instruction Interfaces 4.1.8. Configuring the Custom Instruction Signal Type 4.1.9. Saving and Adding the CRC Custom Instruction 4.1.10. Generating and Compiling the CRC Example System
4.1.7. Setting Up the CRC Custom Instruction Interfaces x
4.1.7.1. Specifying Additional Interfaces
4.2. Building the CRC Example Software x
4.2.1. Running and Analyzing the CRC Example Software 4.2.2. Using the User-defined Custom Instruction Macro
4.2.1. Running and Analyzing the CRC Example Software x
4.2.1.1. Output of the CRC Design Example Software Run on a Cyclone V E FPGA Development Kit using the Intel® Quartus® Prime Software v15.1.
5. Introduction to Nios® II Floating Point Custom Instructions x
5.1. Floating Point Background 5.2. IEEE 754 Format 5.3. Rounding Schemes 5.4. Special Floating Point Cases
5.2. IEEE 754 Format x
5.2.1. Unit in the Last Place 5.2.2. Floating Point Value Encoding
5.3. Rounding Schemes x
5.3.1. Nearest Rounding 5.3.2. Truncation Rounding 5.3.3. Faithful Rounding 5.3.4. Rounding Examples
6. Nios II Floating Point Hardware 2 Component x
6.1. Overview of the Floating Point Hardware 2 Component 6.2. Floating Point Hardware 2 IEEE 754 Compliance 6.3. IEEE 754 Exception Conditions with FPH2 6.4. Floating Point Hardware 2 Operations 6.5. Building the FPH2 Example Hardware 6.6. Building the FPH2 Example Software 6.7. FPH2 Implementation of GCC Options 6.8. Nios II FPH2 and the Newlib Library 6.9. C Macros for round(), fmins(), and fmaxs()
6.6. Building the FPH2 Example Software x
6.6.1. FPH2 and Nios II GCC 6.6.2. Floating Point Hardware 2 Conversions 6.6.3. Nios II FPH2 Software Options
6.6.3. Nios II FPH2 Software Options x
6.6.3.1. -mcustom-<operation> 6.6.3.2. Nios II FPH2 Pragmas 6.6.3.3. -mcustom-fpu-cfg
6.7. FPH2 Implementation of GCC Options x
6.7.1. -fno-math-errno 6.7.2. -fsingle-precision-constant 6.7.3. -funsafe-math-optimizations 6.7.4. -ffinite-math-only 6.7.5. -fno-trapping-math 6.7.6. -frounding-math
7. Nios® II Floating Point Hardware (FPH1) Component x
7.1. Creating the FPH1 Example Hardware 7.2. Adding FPH1 to the Design and Configuring the Device 7.3. Building the FPH1 Example Software 7.4. Nios II FPH1 and the Newlib Library 7.5. Assessing Your Floating Point Optimization Needs 7.6. Hardware Divide Considerations with FPH1
7.3. Building the FPH1 Example Software x
7.3.1. Creating the FPH1 Software Project 7.3.2. Running and Analyzing the FPH1 Example Software 7.3.3. Software Implementation for FPH1
1. Nios II Custom Instruction Overview
2. Custom Instruction Hardware Interface
3. Custom Instruction Software Interface
4. Design Example: Cyclic Redundancy Check
5. Introduction to Nios® II Floating Point Custom Instructions
6. Nios II Floating Point Hardware 2 Component
7. Nios® II Floating Point Hardware (FPH1) Component
8. Document Revision History for Nios II Custom Instruction User Guide

6.1. Overview of the Floating Point Hardware 2 Component

The following figure shows the structure of the FPH2 component, with the display name Floating Point Hardware 2 and the IP name altera_nios_custom_instr_floating_point_2. Floating Point Hardware 2 packages all the floating point functions in a single component, consisting of the following subcomponents:
  • altera_nios_custom_instr_floating_point_2_combi
  • altera_nios_custom_instr_floating_point_2_multi
Figure 21. Custom Instruction ImplementationThis figure lists the floating-operations implemented by each custom instruction.
The characteristics of the FPH2 are:
  • Supports FPH1 operations (add, sub, multiply, divide) and adds support for square root, comparisons, integer conversions, minimum, maximum, negate, and absolute
  • Single-precision floating point values are stored in the Nios II general purpose registers
  • VHDL only
  • Platform Designer support only
  • Single-precision only
  • Optimized for FPGAs with 4-input LEs and 18-bit multipliers
  • GCC and Nios II SBT (Software Build Tools) software support
  • IEEE 754-2008 compliant except for:
    • Simplified rounding
    • Simplified NaN handling
    • No exceptions
    • No status flags
    • Subnormal supported on a subset of operations
  • Binary-compatibility with FPH1
    • FPH1 implements Round-To-Nearest rounding. Because FPH2 implements different rounding, results might be subtly different between the two generations
  • Resource consumption in a typical system:
    • Approximately 2500 4-input LEs
    • Nine 9-bit multipliers
    • Three M9K memories or larger

In Platform Designer, the Floating Point Hardware 2 component is under Embedded Processors on the Component Library tab.

Table 13.  Floating Point Custom Instruction 2 Operation SummaryIn this table, a and b are assumed to be single-precision floating point values.
Operation 4 N 5 Cycles Result Subnormal Rounding GCC Inference
fdivs 255 16 a ÷ b Flush to 0 Nearest a / b
fsubs 254 5 a – b Flush to 0 Faithful a – b
fadds 253 5 a + b Flush to 0 Faithful a + b
fmuls 252 4 a x b Flush to 0 Faithful a * b
fsqrts 251 8   Faithful sqrtf() 6
floatis 250 4 int_to_float(a) Not applicable Not applicable Casting
fixsi 249 2 float_to_int(a) Flush to 0 Truncation Casting
round 248 2 float_to_int(a) Flush to 0 Nearest lroundf()6
Reserved 234 to 247 Undefined Undefined      
fmins 233 1 (a < b) ? a : b Supported None fminf()6
fmaxs 232 1 (a < b) ? b : a Supported None fmaxf() 6
fcmplts 231 1 (a < b) ? 1 : 0 Supported None a < b
fcmples 230 1 (a ≤ b) ? 1 : 0 Supported None a <= b
fcmpgts 229 1 (a > b) ? 1 : 0 Supported None a > b
fcmpges 228 1 (a ≥ b) ? 1 : 0 Supported None a >= b
fcmpeqs 227 1 (a = b) ? 1 : 0 Supported None a == b
fcmpnes 226 1 (a ≠ b) ? 1 : 0 Supported None a != b
fnegs 225 1 -a Supported None -a
fabss 224 1 |a| Supported None fabsf()

The cycles column specifies the number of cycles required to execute the instruction. A combinatorial custom instruction takes 1 cycle. A multi-cycle custom instruction requires at least 2 cycles. An N-cycle multi-cycle custom instruction has N - 2 register stages inside the custom instruction because the Nios II processor registers the result from the custom instruction and allows another cycle for g wire delays in the source operand bypass multiplexers. The number of cycles does not include the extra cycles (maximum of 2) that an instruction following the multi-cycle custom instruction is stalled by the Nios II/f if the instruction uses the result within 2 cycles. These extra cycles occur because multi-cycle instructions are late result instructions

The Nios II Software Build Tools (SBT) include software support for the FPH2 component. When the FPH2 component is present in hardware, the Nios II compiler compiles the software codes to use the custom instructions for floating point operations.

4 These names match the names of the corresponding GCC command-line options except for round, which GCC does not support.
5 Specifies the 8 bit fixed custom instruction for the operation.
6 Nios II GCC version 4.7.3 is not able to reliably replace calls to newlib floating point functions with the equivalent custom instruction even though it has Flush to 0 -mcustom- <operation> command-line options and pragma support for these operations. Instead, the custom instruction must be invoked directly using the GCC __builtin_custom_* facility. The FPH2 component includes a C header file that provides the required #define macros to invoke the custom instruction directly.
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