JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

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ID 683298
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Design Components 1.2.6. Clocking Scheme 1.2.7. Simulation 1.2.8. Design Example Files 1.2.9. Registers 1.2.10. Signals 1.2.11. Customizing the Design Example
1.2.5. Design Components x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker
1.2.5.1. Platform Designer System Component x
1.2.5.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.2. Parallel I/O 1.2.5.1.3. ATX PLL 1.2.5.1.4. Core PLL 1.2.5.1.5. SPI Master
1.2.7. Simulation x
1.2.7.1. Testbench
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.1.4. Compiling and Testing the Design

The JESD204B parameter editor allows you to run the design example on a target development kit.

Perform the following steps to compile the design and program the development board:

  1. Launch the Intel® Quartus® Prime software and compile the design (Processing > Start Compilation).
    The timing constraints and pin assignments for the design example and the design components are automatically loaded during design example compilation.
  2. Connect the development board to the host computer either by connecting a USB cable to the on-board Intel® FPGA Download Cable II component or using an external Intel® FPGA Download Cable II module to connect to the external JTAG connector.
  3. If you are performing external FMC loopback test, attach the FMC loopback card to the FMC port connector.
  4. Launch the Clock Control application that is included with the development board, and set the clock settings according to the selected data rate.
    Note: Refer to the Intel® Cyclone® 10 GX FPGA Development Kit documentation for more information on using the Clock Control application.
    Table 3.  Clock Setting
    Clock Name Clock Frequency
    device_clk Select the frequencies in the PLL/CDR Reference Clock Frequency drop down menu of the IP parameter editor.1
    mgmt_clk 100 MHz
    Figure 4. Clock Control GUI SettingThis example shows the clock control GUI setting for 6.144 Gbps data rate.
  5. Configure the FPGA on the development board with the generated programming file (.sof file) using the Intel® Quartus® Prime Programmer.

Section Content
Board Connectivity
Hardware Test for System Console Control Design Example

Related Information
1 The design example uses 153.6 MHz clock frequency for designs with data rate of 6.144 Gbps.
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