JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

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ID 683298
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Design Components 1.2.6. Clocking Scheme 1.2.7. Simulation 1.2.8. Design Example Files 1.2.9. Registers 1.2.10. Signals 1.2.11. Customizing the Design Example
1.2.5. Design Components x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker
1.2.5.1. Platform Designer System Component x
1.2.5.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.2. Parallel I/O 1.2.5.1.3. ATX PLL 1.2.5.1.4. Core PLL Frame Clock and Link Clock Relationship 1.2.5.1.5. SPI Master
1.2.7. Simulation x
1.2.7.1. Testbench
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.2.5.1.4. Core PLL

The core PLL module generates the clocks for the FPGA core fabric. An IOPLL module is instantiated as core PLL.

The core PLL uses an external clock input as its reference clock to generate two derivative clocks from a single VCO:

  • Link clock
  • Frame clock
Table 11.  Core PLL Ouputs
Clock Formula Description
Link Clock Serial data rate/40 The link clock clocks the JESD204B IP core link layer and the link interface of the transport layer.
Frame Clock Derived based on settings; refer to Table 12. The frame clock clocks the transport layer, test pattern generators and checkers, and any downstream modules in the FPGA core fabric.

For the frame clock, when the F parameter is 1, 2 or 3, the resulting frame clock frequency easily exceeds the capability of the core PLL to generate and close timing. The top level RTL file, (altera_jesd204_ed_<data path>.sv), defines the frame clock division factor parameters, F1_FRAMECLK_DIV (for cases with F = 1) and F2_FRAMECLK_DIV (for cases with F = 2). This factor enables the transport layer and test pattern generator to operate at a divided factor of the required frame clock rate by widening the data width accordingly.

Note: For JESD204B IP design examples, F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2.

As an example, the actual frame clock for a serial data rate of 10 Gbps and F = 1 is: 

(10000/(10 × 1)) / F1_FRAMECLK_DIV = 1000 / 4 = 250 MHz

Frame Clock and Link Clock Relationship

The frame clock and link clock are synchronous. For the derived F mode, the ratio of link_clk period to frame_clk period is given by this formula: 

link_clk period to frame_clk period ratio = 32xL/(MxSxN')
Table 12.  fTXframe and fRXframe for Different F Parameter Settings
  • fTXlink is the TX link clock frequency
  • fRXlink is the RX link clock frequency
F Parameter fTXframe(txframe_clk frequency) fRXframe(rxframe_clk frequency)
1 fTXlinkx(4/F1_FRAMECLK_DIV) fRXlinkx(4/F1_FRAMECLK_DIV)
2 fTXlinkx(2/F2_FRAMECLK_DIV) fRXlinkx(2/F2_FRAMECLK_DIV)
4 fTXlink fRXlink
8 fTXlink/2 fRXlink/2
Level Two Title